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rev. 0.8 9/14 copyright ? 2014 by silicon laboratories an383 an383 si47 xx a ntenna , s chematic , l ayout , and d esign g uidelines 1. introduction this document provides general si47xx design gui delines and am/fm/sw/lw/wb antenna selections which includes schematic, bom, la yout and design checklist. all users should follow the si47xx design guidelines pres ented in section 2 and then users can proceed to the appropriate antenna selections according to the applicati on and device used presented in sections 3 through 10. to get an in-depth knowledge about ea ch individual antenna, the antenna t heory and interface model is presented in the appendices. table 1. supported devices and antennas part number general description function fm antenna wb antenna am/lw antenna sw antenna fm transmitter fm receiver am receiver sw/lw receiver wb receiver headphone embedded cable whip ferrite loop air loop whip SI4700 fm receiver ? ? si4701 fm receiver with rds ? ? si4702 fm receiver ? ? si4703 fm receiver with rds ? ? si4704 fm receiver ? ??? si4705 fm receiver with rds ? ??? si4706 high performance rds receiver ? ??? si4707 wb receiver with same ? ? si4710 fm transmitter ? ?? si4711 fm transmitter with rds ? ?? si4712 fm transmitter with rps ? ?? si4713 fm transmitter with rds & rps ? ?? si4720 fm transceiver ?? ??? si4721 fm transceiver with rds ?? ??? si4730 am/fm receiver ?? ? ?? si4731 am/fm receiver with rds ?? ??? si4734 am/sw/lw/fm receiver ??? ? ??? si4735 am/sw/lw/fm receiver with rds ??? ???? si4736 am/fm/wb receiver ?? ?? ??? si4737 am/fm/wb receiver with rds ?? ?? ??? si4738 fm/wb receiver ? ?? ? si4739 fm/wb receiver with rds ? ?? ? si4784 fm receiver ??? si4785 fm receiver with rds ???
an383 2 rev. 0.8
an383 rev. 0.8 3 t able of c ontents section page 1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2. si47xx 3x3 mm qfn schematic and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.1. si47xx 3x3 mm design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.2. emissions mitigation com ponents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.3. si47xx 3x3 mm schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.4. si47xx 3x3 mm bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5. si47xx 3x3 mm layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6. si47xx 3x3 mm design checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3. headphone antenna for fm recei ver on fmi (si470x/2x/3x/8x only) . . . . . . . . . . . . . . 18 3.1. headphone antenna design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2. headphone antenna schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3. headphone antenna bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4. headphone antenna layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5. headphone antenna design che cklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4. cable antenna for fm receive on fmi (si470x/2x/3x/8x only) . . . . . . . . . . . . . . . . . . . 22 4.1. cable antenna design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2. cable antenna schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3. cable antenna bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4. cable antenna layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5. cable antenna design checkl ist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5. embedded antenna for fm transmit on tx o and receive on lpi (si4704/05/06/1x/2x only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1. embedded antenna desi gn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2. embedded antenn a schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3. embedded antenn a bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4. embedded antenn a layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.5. embedded antenna de sign checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6. cable antenna for fm tran smit on txo and receive on lpi (si4704/05/06/1x/2x only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.1. cable antenna design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2. cable antenna schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3. cable antenna bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4. cable antenna layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.5. cable antenna design checkl ist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7. whip antenna for fm/wb receiver on fmi (si4707/3x only) . . . . . . . . . . . . . . . . . . . . .37 7.1. fm/wb whip antenna design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2. fm/wb whip antenna schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3. fm/wb whip antenna bill of materi als . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 7.4. fm/wb whip antenna layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 7.5. fm/wb whip antenna design checklis t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8. ferrite loop antenna for am/lw receive on am i (si4730/31/34/35/36/37 only) . . . . . 39
an383 4 rev. 0.8 8.1. ferrite loop antenna design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.2. ferrite loop antenna schemat ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.3. ferrite loop antenna bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.4. ferrite loop antenna layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.5. ferrite loop antenna design checklis t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 9. air loop antenna for am/lw receive on ami (si4730/31/34/35/36/ 37 only) . . . . . . . . 42 9.1. air loop antenna design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 9.2. air loop antenna schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3. air loop antenna bill of mate rials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.4. air loop antenna layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.5. air loop antenna design che cklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10. whip antenna for sw receive on ami (si4734/35 only) . . . . . . . . . . . . . . . . . . . . . . . 45 10.1. sw whip antenna design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2. sw whip antenna schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.3. sw whip antenna bill of material s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.4. sw whip antenna layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.5. sw whip antenna design checklis t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 appendix a?fm receive headphone antenna interface m odel . . . . . . . . . . . . . . . . . . . . 50 appendix b?fm transmit embedded antenna interface model . . . . . . . . . . . . . . . . . . . 55 appendix c?am ferrite loop stick an tenna interface model . . . . . . . . . . . . . . . . . . . . . 63 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
an383 rev. 0.8 5 2. si47xx 3x3 mm qfn schematic and layout this section shows the minimal schematic and layout op tions required for optimal si47xx performance. population options are provided to support a si ngle layout for all 3 x 3 mm qfn devices, mitigate system noise, operate the internal oscillator with an external crystal, and filter vco energy. 2.1. si47xx 3x3 mm design c1 (22 nf) is a required bypass capacitor for vd/vdd suppl y pin 11. place c1 as close as possible to the vd/vdd pin 11 and gnd pin 12. place a via connecting c1 vd/vdd supply to the power rail such that the cap is closer to the si47xx than the via. route c1 gnd directly and only to gnd pin 12 with a wide, low inductance trace. c1 gnd should not be routed to gnd via. these recommendations are made to reduce the size of the current loop created by the bypass cap and routing, minimize bypass cap impedance and return all currents to the gnd pad. note: for si47xx rev d parts, c1 is required on pin 11 (va ). the c1 design guidelines described above should be followed. for an illustration of these guidelines, refer to figure 3. c2 (22 nf) is an optional bypass capacitor for va/lin/d fs supply pin 16 (si4702/03 only) and may be placed to mitigate supply noise. place c2 as close as possibl e to the va/lin/dfs pin 16 and gnd pin 15. place a via connecting c2 va supply to the powe r rail such that the cap is closer to the si47xx than the via. route c2 gnd directly and only to gnd pin 15 with a wide, low inductance trace. route g nd/rin/dout pin 15 to the gnd pad if designing only for the si4702/03. if designing for all si47xx devices, do not route g nd/rin/dout pin 15 to the gnd pad. in this case the on-chip connection between pin 15 and the gn d pad will provide a ground connection. these recommendations are made to reduce the size of the current loop created by the bypass cap and routing, minimize bypass cap impedance and return all currents to the gnd pad. c3 (100 nf) is an optional bypass capacitor for the vio su pply pin 10 and may be placed to mitigate supply noise. place c3 as close as possible to the vi o pin 10 and the gnd pin 12. place a via connecting c3 vio supply to the power rail such that the cap is closer to the si47xx than the via. route c3 gnd directly and only to gnd pin 12 with a wide, low inductance trace. c3 gnd should not be routed to gnd via. these recommendations are made to reduce the size of the current loop created by the bypa ss cap and routing, minimize bypass cap impedance and return all currents to the gnd pad. note: for si47xx rev d parts, c3 is required on pin 10 (vd) . the c3 design guidelines described above should be followed. c6 and c7 (0.39f) are ac coupling caps for transmitter audio input to va/lin/dfs pin 16 and gnd/rin/dout pin 15 (si471x/2x analog audio input mode only). the input resistance of the transmitter audio in put and the cap will set the high pass pole given by equation 1. the input re sistance of the audio input is programmatically selectable as 396 k ? , 100 k ? , 74 k ? , or 60 k ? (default). placement location is not critical. equation 1. high-pass pole calculation c8 and c9 (0.39 f.) are ac coupling caps for receiver analog audio output from rout/din pin 13 and lout/dfs pin 14 (si470x/2x/3x/8x audio output mo de only). the input resistance of the amplifier, such as a headphone amplifier, and the capacitor will determine the high pass pole given by equation 1. placement location is not critical. c10 and c11 (7?22 pf) are optional crystal loading caps required only when using the internal oscillator feature. refer to the crystal data sheet for the proper load capaci tance and be certain to account for parasitic capacitance. place caps c10 and c11 such that they share a common gnd connection and the current loop area of the crystal and loading caps is minimized. c12 and c13 (2.2 pf) are noise mitigation caps if digital audio option is in use. the caps need to be placed close to the si47xx chip. x1 (32.768 khz) is an optional crystal required only when using t he internal oscillator feature. place the crystal x1 as close to gpo3/dclk pin 17 and rclk pin 9 as possible to minimize current loops. route the rclk trace as far from sdio pin 8 and sdio trace as poss ible to minimize capacitive coupling. r1 (0 ? ) is an optional jumper used to route the digital audio clock to gpo3/dclk pin 17. r1 is only required for a universal design which accommodates bom population options selecting between crystal and digital audio (si4705/06/1x/2x/31/35/37/39/8x only). f c 1 2 ? rc --------------- - =
an383 6 rev. 0.8 note: crystal and digital audio mode cannot be used at the same ti me. populate r1 and remove c10, c11, and x1 when using digital audio. populate c10, c11, and x1 an d remove r1 when using the internal oscilla tor. place resistor r1 as close to dclk/ gpo3 pin 17 as possible as shown in layout example 4 to minimize trace length from pin 17 to the crystal and load cap. r2-r6 (25 ? ?2 k ? ) are optional series termination resistors and are used to mitigate system noise. the recommended value of the resistors is 2 k ? for optimal edge rate and noise suppression. confirm that timing requirements are met with the selected series termination resistor value. place the series termination resistors r2- r6 as close to the host controller as possible. r7 and r8 (4.7 k ? ) are optional pull-up resistors for the sclk and sdio lines required only when using an i 2 c bus. the size of pull-up resi stor value will vary based on the number of devices, capa citance and spee d of the bus. placement location is not critical. refer to the i 2 c specification for additi onal design information. r9 (0 ? ) is used to route power to va/lin/dfs supply pin 16. r9 is only required to support a layout for all 3x3 mm qfn devices. if designing for the si4702/03 only r9 ma y be replaced with trace connections. if designing for si4704/05/06/07/1x/2x/3x/8x only, r9 is not required. place resistor r9 as cl ose to va/lin/dfs pin 16 as possible. r10 (0 ? ) is an optional jumper used to route the va pin 16 for si4702/03. r10 is only required for a universal design which supports bom options for the si4702/03 an d other si47xx devices. r10 should be populated when using an si4702/03 and not populated when using an alternate device. r11 (0 ? ) is an optional jumper used to route the dfs to va/lin/dfs pin 16. r11 is only required for a design in which the si4702/03 and digital audio output (si4705/0 6/21/31/35/37/39/8x) bom op tions are desired. place resistor r11 as close to pin va/lin/dfs 16 as possible. r12 (25 ? ?2 k ? ) is a required series termination resistor when using digital audio output (si4705/06/21/31/35/37/ 39/8x) and is used to mitigate noise from the digital data routed from gnd/rin/dout pin 15. the recommended value of the resistor is 604 ? for optimal edge rate and noise suppression. confirm that timing requirements are met with the selected series termination resistor value. place r12 as close to pin 15 as possible. r13 (25 ? ?2 k ? ) is a required series termination resistor when using digital audio (si4705/06/1x/2x/31/35/37/39/8x only) and is used to mitigate noise from the digital clock routed to gpo3/dclk pin 17. the recommended value of the resistor is 2 k ? for optimal edge rate and noise suppression. conf irm that timing requirements are met with the selected series termination resistor value. place r13 as close to the host controller as possible. r14 (25 ? ?2 k ? ) is a required series termination resistor when using digital audio output (si4705/06/21/31/35/37/ 39/8x) and is used to mitigate noise from the digital frame clock routed to va/lin/dfs pin 16. the recommended value of the resistor is 2 k ? for optimal edge rate and noise suppression. confirm that timing requirements are met with the selected series termination resistor value. place r14 as close to the host controller as possible. r15 (25 ? ?2 k ? ) is a required series termination resistor when using digital audio input (si471x/2x only) and is used to mitigate noise from the digital frame clock ro uted to lout/dfs pin 14. the recommended value of the resistor is 2 k ? for optimal edge rate and noise suppression. co nfirm that timing requirements are met with the selected series termination resistor value. place r15 as close to the host controller as possible. r16 (25 ? ?2 k ? ) is a required series termination resistor when using digital audio input (si471x/2x only) and is used to mitigate noise from the digital data routed to rout/din pin 13. the recommended value of the resistors is 2k ? for optimal edge rate and noise suppression. confirm that timing requirements are met with the selected series termination resistor value. place r16 as close to the host controller as possible. r17 (0 ? ) is an optional jumper used to route the gnd pin 15 for si4702/03. r17 is only required for a universal design which supports bom options for the si4702/03 an d other si47xx devices. r17 should be populated when using an si4702/03 and not populated when using an al ternate device. place r17 as close to the si47xx as possible. r18 (0 ? ) is an optional jumper used to route the gnd pin 4 for si4702/03. r18 is only required for a universal design which supports bom options for the si4702/03 an d other si47xx devices. r18 should be populated when using an si4702/03 and not populated when using an al ternate device. place r18 as close to the si47xx as possible.
an383 rev. 0.8 7 2.2. emissions mi tigation components the following components may be placed to reduce vco emissi ons. this is only requir ed if regulatory testing requires measuring emissions at the vco frequency of 3?4 ghz. refer to section ?2 .6.1. emissions mitigation checklist? for detailed layout and grounding recommendations pertaining to the components described below. 2.2.1. fmi mitigation components c5 (np) is an optional filter capacitor for fmi pin 2 and may be placed to shunt vco energy to gnd and prevent it from radiating from an antenna connected to the fmi pin. this pad is a placeholder for alternate emission mitigation option 2. while it is recommended to select option 1 for best sensitivit y and mitigation performance, leaving this pad ensures that there is no redesign nece ssary between options. route pin 2 to gnd/rfgnd if the pin functionality is not used. f1 (blm15ga750sn1) is an optional bead for fmi pin 2 and may be placed to prevent vco energy from radiating from fmi pin. place f1 as close as possible to fmi pin 2. route pin 2 to gnd/rfgnd if the pin functionality is not used. c14 (6 pf) is an optional filter capacitor for fmi pin 2 and may be placed to shunt vco energy to gnd and prevent it from radiating from an antenna connected to the fmi pin. place c14 as close as possible to fmi pin 2. the ground path should be optimized on the top layer. route pin 2 to gnd/rfgnd if the pi n functionality is not used. 2.2.2. ami mitigation components c17 (3.3 pf) is an optional filter capacitor for ami pin 4 on si473x devices and may be placed to shunt vco energy to gnd and prevent it from radiating from an antenna connected to the ami pin. place c17 as close as possible to ami pin 4 and rfgnd pin 3. the ground path should be op timized on the top layer. route pin 4 to gnd/rfgnd if the pin functionality is not used. l2 (10 nh) is an optional filter inductor for ami pin 4 on si473x devices and may be placed to prevent vco energy from radiating from ami pin. place l2 as close as possible to ami pin 4. route pin 4 to gnd/rfgnd if the pin table 2. fmi mitigation components option components sensitivity mitigation cost 1c5 = np f1 = blm15ga750sn1 c14 = 6 pf best best higher 2c5 = 2.7pf f1 = 20 nh c14 = 2.7 pf less (+1.75 db vs option1) good lower table 3. ami mitigation components option components sensi tivity mitigation cost 1 c17 = 3.3 pf l2 = 10 nh c16 = 3.3 pf best good lower 2 c17 = 2.7 pf l2 = 20 nh c16 = 2.7 pf less (+3 db vs option1) better lower 3c17 = np l2 = blm15ga750sn1 c16 = np least (+6 db vs option1) best higher
an383 8 rev. 0.8 functionality is not used. c16 (3.3 pf) is an optional filter capacitor for ami pin 4 on si473x devices and may be placed to shunt vco energy to gnd and prevent it from radiating from an antenna connected to the ami pin. place c16 as close as possible to ami pin 4 and rfgnd pin 3. the ground path should be op timized on the top layer. route pin 4 to gnd/rfgnd if the pin functionality is not used. 2.2.3. gpio mitigation components c15 (33 pf) is an optional filter capacitor for gpo1 pi n 19 and may be placed to shunt vco energy to gnd and prevent it from radiating. place c15 as close as possible to gpo1 pin 19. the ground path should be optimized on the top layer. r20 (330 ? ) is an optional mitigating resistor for gpo1 pin 19 and may be placed to prevent vco energy from radiating from gpo1 pin. place r20 as close as possible to gpo1 pin 19. r20 is not required if gpo1 is pulled up/ down by design and has no other connections. c18 (33 pf) is an optional filter capacitor for gpo2 pin 18 and may be placed to shunt vco energy to gnd and prevent it from radiating. place c18 as close as possible to gpo2 pin 18. the ground path should be optimized on the top layer. r19 (330 ? ) is an optional mitigating resistor for gpo2 pin 18 and may be placed to prevent vco energy from radiating from gpo2 pin. place r19 as close as possible to gpo2 pin 18. r19 is not required if gpo2 is pulled up/ down by design and has no other connections. 2.2.4. lpi mitigation components c4 (3.3 pf) is an optional filter capacitor for txo/lp i pin 4 on si4704/05/06/1x/2x dev ices and may be placed to shunt vco energy to gnd and prevent it from radiati ng from an antenna connecte d to the txo/lpi pin. make measurements with different c4 and l1 values in-system to optimize the filter?s performan ce for the antenna design chosen. place c4 as close as possible to txo/lpi pin 4 and rfgnd pin 3. the ground path should be optimized on the top layer. route pin 4 to g nd/rfgnd if the pin func tionality is not used. l1 (15 nh) is an optional filter inductor for txo/lpi pi n 4 on si4704/05/06/1x/2x de vices and may be placed to prevent vco energy from radiating from an antenna co nnected to the txo/lpi pin. make measurements with different c4 and l1 values in-system to optimize the f ilter?s performance for the antenna design chosen. place l1 as close as possible to txo/lpi pin 4. route pin 4 to gnd/rfgnd if the pin functionality is not used. table 4. gpio mitigation components option components sensi tivity mitigation cost 1 c15 = 33 pf r20 = 330 ? c18 = 33 pf r19 = 330 ? best best low 2 c15 = 33 pf r20 = 330 ? c18 = np r19 = 330 ? best good low table 5. lpi mitigation components option components sensitivity mitigation cost 1c4 = 3.3pf l1 = 15 nh best best low
an383 rev. 0.8 9 2.3. si47xx 3x3 mm schematic figure 1. si47xx 3x3 mm qfn schematic
an383 10 rev. 0.8 2.4. si47xx 3x3 mm bill of materials the required bill of materials fo r figure 1 is shown in table 6. the optional bill of materials for figure 1 is shown in table 7. table 6. required bill of materials designator description note c1 vd/vdd supply bypass capacitor, 22 nf, 10%, z5u/x7r c3 vi0 supply bypass capacitor, 100 nf, 10%, z5u/x7r for supply noise mitigation. optional for si47xx rev c and earlier parts. for si47xx rev d parts, c3 is required. r12 dout current limiting resistor, 604 ? for digital audio output (si4705/06/21/31/35 /37/39/8x only) r13 dclk current limiting resistor, 25 ? ?2 k ? for digital audio (si4705/06/1x/2x/31/35/37/39/8x only) r14 dfs current limiting resistor, 25 ? ?2 k ? for digital audio output (si4705/06/21/31/35 /37/39/8x only) r15 dfs current limiting resistor, 25 ? ?2 k ? for digital audio input (si471x/2x only) r16 din current limiting resistor, 25 ? ?2 k ? for digital audio input (si471x/2x only) u1 silicon laboratories si47xx, 3x3 mm, 20 pin, qfn table 7. optional bill of materials designator description note c2 va supply bypass capacitor, 22 nf, 10%, z5u/x7r for supply noise mitigation (si4702/03 only) c6, c7 ac coupling capacitor, 0.39 f, x7r/x5r for analog audio input (si471x/2x only) c8, c9 ac coupling capacitor, 0.39 f, x7r/x5r for analog audio output c10, c11 crystal load capacitor, 22 pf , 5%, c0g for internal oscillator option c12, c13 noise mitigation capacitor 2.2 pf, c0g for dfs noise mitigation purpose r2?r6 current limiting resistor, 25?2 k ? for digital system noise mitigation r7,r8 pullup resistor, 4.7 k ? for i 2 c bus mode communication r1, r9, r10, r11, r17, r18 0 ? jumper for universal layout design supporting all si47xx x1 crystal, epson fc-135 for internal oscillator feature
an383 rev. 0.8 11 table 8. optional bill of materials: emissions mitigation designator description note c4 vco filter capacitor 3.3 pf, 0402, c0g for filtering of vco energy (si4704/05/06/1x/2x only) c5 vco filter capacitor np, 0402, c0g placeholder pad for alternate fmi vco filter configuration c14 vco filter capacitor 6 pf, 0402, c0g for filtering of vco energy c15, c18 vco filter capacitor 33 pf, 0402, c0g for filtering of vco energy c16, c17 vco filter capacitor 3.3 pf, 0402, c0g for filtering of vco energy (si473x only) f1 vco filter bead murata blm15ga750sn1 for filtering of vco energy l1 vco filter inductor 15 nh (murata lqw18anr15nj00d) for filtering of vco energy (si4704/05/06/1x/2x only) l2 vco filter inductor 10 nh (murata lqw18an10nj00d) for filtering of vco energy (si473x only) r19, r20 vco mitigating resistor, 330 ? , 0402 for filtering of vco energy
an383 12 rev. 0.8 2.5. si47xx 3x3 mm layout the following layout example selector guide provides guidance for selecting the proper example based on placement, routing, option, and device requirements. lay out examples 1, 2, and 3 show the critical component layout of the most common layout configurations. layout example 4 shows a universal layout which supports all 3x3 mm qfn devices and features. table 9. layout example selector guide by place and route requirements placement and routing layout example 1234 top side routing x x x x inner/bottom side routing x x x x top side placement x x x x bottom side placement x x table 10. layout example selector guide by option feature layout example 1234 crystal x x x analog input x x analog output x x x x digital input x x digital output x x table 11. layout example selector guide by device device layout example 1234 si4702/03 x x x si4704/05/06/07 x x x x si471x x x si472x x x x x si473x x x x x si478x x x x x
an383 rev. 0.8 13 the following layout rules are used: ? layer 1 top side placement and routing (shown) ? layer 2 gnd (not shown) ? power routed by trace (not shown) ? 0402 component size or larger ? 6 mil traces ? 6 mil trace spacing ? 15 mil component spacing figure 2 shows critical component layout with top side placement, top and bottom side routing, crystal and analog output support, and support for all devices except the si 471x transmitter family. the si471x transmitter family can be supported in this example if va bypass cap c2 is remo ved and audio input is routed to pin 15 and pin 16. digital audio is not available when the crystal is used due to the multipurpose role of gpo3/dclk pin 17. vio bypass cap c3 is not included in this example in order to optimize routing of the crystal oscillator. route the rclk trace as far from the sdio pin 8 and trace as possible by routing the sdio trace on the bottom layer. if bottom side placement is possible, figure 3 is preferred for optimal oscilla tor performance. f1, c14, c15, c18, r19 and r20 are pl aced as close to the chip as possi ble. for the si4704/05/06/2x with the short antenna option, pin 4 is populated with l1 and c4, c1 7 is not populated; for the si473x am receiver, c4 is replaced with c16, l1 is replac ed with l2, and c17 is populated. figure 2. layout example 1 figure 3 shows critical component layout with top and bottom side placement, top and bottom side routing, crystal and analog output support, and support for all devices exce pt the si471x transmitter family. the si471x transmitter family can be supported in this example if va bypass cap c2 is removed and audio input is routed to gnd/rin/ dout pin 15 and va/lin/dfs pin 16. digital audio is not available when the crystal is used due to the multipurpose role of gpo3/dclk pin 17. route the rclk trace as far from the sdio pin 8 and trace as possible by routing the rclk trace on the bott om layer. this example is preferred for optimal oscillator pe rformance. f1, c14, c15, c18, r19, and r20 are placed as close to the chip as possible. for the si4704/05/06/2x with the short antenna option, pin 4 is populated with l1 and c4, c1 7 is not populated; for the si473x am receiver, c4 is replaced with c16, l1 is replac ed with l2, and c17 is populated.
an383 14 rev. 0.8 figure 3. layout example 2 figure 4 shows critical component layout with top and bottom side placement, top and bottom side routing, analog and digital input and output support, and support for all devices except the si4702/03 receiver family. the si4702/ 03 receiver family can be supported in this example if the va supply is routed to va/lin/dfs pin 16 and r12 is removed. the crystal is not available when digital audio is used due to the multipurpose role of gpo3/dclk pin 17. note that the rclk trace is not a sensitive node w hen an external reference clock is used instead of the crystal. for this reason, an external refere nce clock allows more routing flexibility. f1, c14, c15, c18, r19, and r20 are placed as close to the chip as possible. for the si4704/05/06/2x with the short antenna option, pin 4 is populated with l1 and c4, c1 7 is not populated; for the si473x am receiver, c4 is replaced with c16, l1 is replac ed with l2, and c17 is populated. figure 4. layout example 3 p p
an383 rev. 0.8 15 figure 5 shows critical component layout with top and bottom side placement, top and bottom side routing, crystal support, analog and digital input and output support, and suppo rt for all devices. for this reason it is referred to as a universal layout. either crystal or digital audio operation must be selected due to the multipurpose role of gpo3/ dclk pin 17. note that the rclk trace is not a sensitive node when an external reference clock is used instead of the crystal. for this reason, an extern al reference clock allows more routi ng flexibility. to support the crystal oscillator feature, route the rclk trace as far from th e sdio pin 8 and trace as possible by routing the rclk trace on the bottom layer. f1, c14, c15, c18, r19 and r20 are pl aced as close to the chip as possi ble. for the si4704/05/06/2x with the short antenna option, pin 4 is populated with l1 and c4, c1 7 is not populated; for the si473x am receiver, c4 is replaced with c16, l1 is replac ed with l2, and c17 is populated. figure 5. layout example 4 place a ground plane under the si47xx as shown in fi gure 6, ?two layer stackup? or figure 7, ?four layer stackup?. for designs in which a continuous ground plane is not possible, place a local ground plane directly under the si47xx. do not route signal traces on the ground layer under the si47xx and do not route signal traces under the si47xx without a ground plane between the si47xx and signal trace. flood the primary and secondary layers with ground and place stitching vias to create a low impedance connection between planes. do not route digital or rf traces over breaks in the gr ound plane. route all traces to minimize inductive and capacitive coupling by keeping digital traces away from analog and rf traces, minimi zing trace length, minimizing parallel trace runs, and keeping current loops small. in particular, care should be taken to avoid routing digital signals or reference clock traces near or parallel to th e vco pins 1, 20 or lout/rout pins 14, 13. digital traces should be routed in between ground planes (on the inner la yers) for best performance. if that is not possible, route digital traces on the opposite side of the chip. route all gnd (including rfgnd) pins to the ground pad. the ground pad should be connected to the ground plane using multiple vias to minimize ground potent ial differences. the except ion is gnd/rin/dout when designing for a universal layout. route power to the si47xx by trace, ensuring that each trace is rated to handle the required current. some trace impedance is preferable so that the decoupling currents are forced to flow through decoupling caps c1, c2, and c3 directly to the ground pins and not by alternate pathways. place the si47xx close to the antenna(s) to minimize antenna trace length and capacitance and to minimize inductive and capacitive coupling. this recommendation mu st be followed for optimal device performance. route the antenna trace over an unobstructed ground plane to minimize antenna loop area and inductive coupling. design, place, and route other circuits such that radiation in the band of interest is minimized. p
an383 16 rev. 0.8 figure 6. two layer stackup figure 7. four layer stackup 2.6. si47xx 3x3 mm design checklist the following design checklist summarizes th e guidelines presented in this section: ? place bypass caps c1, c2 and c3 as close as possible to the supply and ground pins. ? place a via connecting c1, c2, and c3 to the power supp lies such that the cap is between the si47xx and the via. ? route a wide, low inductance return current path from the c1, c2, and c3 to the si47xx gnd pins. ? route gnd/lin/dout pin 15 to the gnd pad if designing only for the si4702/03. ? route c1 gnd directly and only to gnd pin 12. do not connect gnd via to c1. ? place resistor r1 as close to pin gpo3/dclk 17 as possible. ? place r9 as close as possible to va/lin/dfs pin16 as possible. ? place resistor r11 as close to pin va/lin/dfs 16 as possible. ? place resistor r12 as close to pin gnd/rin/dout 15 as possible. ? place the series termination resist ors r2?r6, r13?r16 as close to the host controller as possible. ? place caps c12 or c13 close to the chip if digital audio is used. ? place the crystal x1 as close to gpo3/dclk pin 17 and rclk pin 9 as possible. ? route the sdio trace and rclk trace as far away fr om each other as possible when using crystal x1. ? place caps c10 and c11 such that they share a common gnd connection. ? place a ground plane under the device as shown in fi gure 6, ?two layer stackup? or figure 7, ?four layer stackup?. ? place a local ground plane directly under the device for designs in which a continuous ground plane is not possible. ? route all traces to minimize inductive and capacitive coupling by keeping digital traces away from analog and rf traces, minimizing trace length, minimizing parallel trace runs, and keeping current loops small. ? route digital traces in between ground plane for best perfor mance. if that is not possible, route digital traces on the opposite side of the chip. ? route all gnd (including rfgnd) pins to the ground pad. the ground pad should be connected to the ground plane using multiple vias minimize ground potential differences. the excepti on is gnd/rin/dout when designing for the universal layout. ? route power to the si47xx by trace, ensuring that each trace is rated to handle the required current. ? do not route signal traces on the ground layer directly under the si47xx. ? do not route signal traces under the si47xx without a ground plane between the si 47xx and signal trace. ? do not route digital or rf traces over breaks in the ground plane. ? do not route digital signals or reference clock traces near to the vco pin 1 and 20 or the lout/rout output pin 14 and 13. layer 2 ? ground layer 1 ? primary layer 1 ? primary layer 2 ? ground layer 3 ? route layer 4 ? secondary
an383 rev. 0.8 17 ? do not route vco pin 1 and 20 (nc). these pins must be left floating to guarantee proper operation. ? place the si47xx close to the antenna(s) to minimize antenna trace length and capacitance and to minimize inductive and capacitive coupling. this recommendati on must be followed for optimal device performance. ? route the antenna trace over an unobstructed ground plane to minimize antenna loop area and inductive coupling. ? design, place, and route other circuits such that radiation in the band of interest is minimized. ? tie unused pin(s) to gnd, but do not tie no connect (nc) pins to gnd. for example, in si471x fm transmitter analog audio input mode, dfs pin 14 and din pin 13 are not used; therefore, these two pins should be tied to gnd. 2.6.1. emissions mitigation checklist the following design checklist summari zes the guidelines for mitigating emissions in the 3?4 ghz range, if applicable. ? place f1 as close as possible to fmi pin 2. ? place c14 as close as possible to fmi pin 2. ? place c5 even though it is designated as np, it should be as close as possible to fmi pin2. ? on the si4704/05/06/1x/2x products: ?? place c4 as close as possible to lpi/txo pin 4 and rfgnd pin 3. ?? place l1 as close as possible to lpi/txo pin 4. ? on si473x products: ?? place c16 as close as possible to ami pin 4 and rfgnd pin 3. ?? place l2 as close as possible to ami pin 4. ?? place c17 as close as possible to ami pin 4 and rfgnd pin 3. ? place c15 and c18 as close as possible to gpo1 & gpo2 pins. ? place r19 and r20 as close as possible to gpo1 & gpo2 pins. ? route fmi pin 2 to gnd/rfgnd if the pin functionality is not used. ? route txo/ami/lpi pin 4 to gnd/rfgnd if the pin functionality is not used. ? flood the primary and secondary laye rs with ground and place stitching vias between the gnd fill and gnd plane. ? shunt capacitors c4, c5, c14, c15, c16, c17, and c18 should be connected directly to the gnd plane on top layer. ? do not use heat relief for these pad's gnd connection. ? connecting shunt capacitors only to a via to the gnd pl ane is not sufficient; though it is permissible to have such a via if the top gnd plane is also connected. ? if additional space is available, increase the size of rfgnd trace by moving fmi and ami signal paths further apart. ? avoid unnecessary breaks in the to p ground fill between the si47xx and th e system gnd conn ection. the goal is to have the path from shunt capacitors as direct, unbroken, and wide as possible. ? rotate the si47xx (as necessary) in order to create th e best ground path for the fmi and gpo mitigation as these are the greater contributors to emissions. ? orient the shunt capacitor(s) on fmi (c14) to the right of the trace (towards pin 1). ? orient the shunt capacitors on ami (c16 & c17) to the right of the trace (toward rfgnd, pin 3).
an383 18 rev. 0.8 3. headphone antenna for fm rece iver on fmi (si4 70x/2x/3x/8x only) the si470x/2x/3x fm receiver component supports a headphone antenna interface through the fmi pin. a headphone antenna with a length between 1.1 and 1.45 m suits the fm applicatio n very well because it is approximately half the fm wave length (fm wavelength is ~3 m). 3.1. headphone antenna design a typical headphone cable will contain th ree or more conductors. the left and right audio channels are driven by a headphone amplifier onto left and right audio conductors and the common audio conductor is used for the audio return path and fm antenna. additional conductors may be used for microphone audio, switching, or other functions, and in some app lications the fm antenna will be a separate conductor within the cable. a representation of a typical application is shown in figure 8, ?typical headphone antenna application?. figure 8. typical headphone antenna application si47xx antenna left right ferrite beads
an383 rev. 0.8 19 3.2. headphone antenna schematic figure 9. headphone antenna schematic the headphone antenna implementation requires components l match , c4, f1, and f2 for a minimal implementation. the esd protection diodes and headpho ne amplifier components are system components that will be required for proper implementation of any tuner. inductor l match is selected to maximize the voltage gain across the fm band. l match should be selected with a q of 15 or greater at 100 mhz and minimal dc resistance. ac-coupling capacitor c4 is used to remove a dc offset on the fmi input. this capacitor must be chosen to be large enough to cause negligible loss with an lna input capacitance of 4?6 pf. the recommended value is 100 pf?1 nf. ferrite beads f1 and f2 provide a low-impedance a udio path and high-impedance rf path between the headphone amplifier and the headphone. ferrite beads should be placed on each antenna conductor connected to nodes other than the fmip such as left and right audio, microphone audio, switching, etc. in the example shown in figure 9, these nodes are the left and right audio conductors. ferrite beads should be 2.5 k ? or greater at 100 mhz, such as the murata blm18bd252sn1. high re sistance at 100 mhz is desirable to maximize r shunt , and therefore, r p . refer to " appendix a?fm receive headphone antenna interface model" on page 50 for a complete description of r shunt , r p , etc. esd diodes d1, d2, and d3 are recommended if design requirements exceed the esd rating of the headphone amplifier and the si47xx. diodes should be chosen with no more than 1 pf parasitic capacitance, such as the california micro devices cm1210. diode capacitance should be minimized to minimize c shunt , and therefore, c p . if d1 and d2 must be chosen with a capacitance greater than 1 pf, they should be placed between the ferrite beads f1 and f2 and the headphone amplifier to minimize c shunt . this placement will, however, reduce the effectiveness of the esd protection devices. diode d3 may not be relocated and must therefore have a capacitance less than 1 pf. note that each diode packag e contains two devices to pr otect against positive and negative polarity esd events. c9 and c10 are 125 f ac coupling capacitors required when the audio amplifier does not have a common mode output voltage and the audio output is swinging above and below ground. optional bleed resistors r5 and r6 may be desirable to discharge the ac-coupling capacitors when the headphone cable is removed.
an383 20 rev. 0.8 optional rf shunt capacitors c5 and c6 may be placed on the left and right audio traces at the headphone amplifier output to reduce the level of digital noise passed to the antenna. the recommended value is 100 pf or greater, however, the designer should confirm that the headphone amplifier is capable of driving the selected shunt capacitance. this schematic example uses the national semiconductor lm4910 headphone amplifier. passive components r1? r4 and c7?c8 are required for the lm4910 headphone amplifier as described in the lm4910 data sheet. the gain of the right and left amplifiers is ?r3/r1 and ?r4/r2, re spectively. these gains can be adjusted by changing the values of resistors r3 and r4. as a general guide, gain between 0.6 and 1.0 is recommended for the headphone amplifier, depending on the gain of the headphone elements. capacitors c7 and c8 are ac-coupling capacitors required for the lm4910 interface. these capacitors, in conjunction with resistors r1 and r2, create a high-pass filter that sets the audio amplifier' s lower frequency limit. the high-pass corner frequencies for the right and left amplifiers are: with the specified bom components, the corner frequen cy of the headphone amplifie r is approximately 20 hz. capacitor c1 is the supply bypass capacitor for the audio amplifier. the lm4910 can also be shut down by applying a logic low voltage to the number 3 pin. the ma ximum logic low level is 0.4 v and the minimum logic high level is 1.5 v. the bill of materials for the typical ap plication schematic shown in figure 6 is provided in t able 12. note that manufacturer is not critical for resistors and capacitors. 3.3. headphone antenna bill of materials table 12. headphone antenna bill of materials designator description note lmatch ind, 0603, sm, 270 nh, murata, lqw18anr27j00d c4 ac coupling cap, sm, 0402, x7r, 100 pf d1, d2, d3 ic, sm, esd diode, sot23-3, california micro devices, cm1210-01st u3 ic, sm, headphone amp, national semiconductor, lm4910ma r1, r2, r3, r4 res, sm, 0603, 20 k ? c7, c8 cap, sm, 0603, 0.39uf, x7r c5, c6 cap, sm, 0402, c0g, 100 pf r5, r6 res, sm, 0603, 100 k ? f1, f2 ferrite bead, sm, 0603, 2.5 k ? , murata, blm18bd252sn1d c1 cap, sm, 0402, x7r, 0.1 f r7 res, sm, 0402, 10 k ? f cright 1 2 ? r1 c7 ?? ------------------------------- - f cleft 1 2 ? r2 c8 ?? ------------------------------- - = ? =
an383 rev. 0.8 21 3.4. headphone antenna layout to minimize inductive and capacitive coupling, inductor l match and headphone jack j24 should be placed together and as far from noise sources such as cl ocks and digital circuits as possible. l match should be placed near the headphone connector to keep audio currents away from the si47xx. to minimize c shunt and c p , place ferrite beads f1 and f2 as close as possible to the headphone connector. to maximize esd protection diode ef fectiveness, place diodes d1, d2 an d d3 as close as possible to the headphone connector. if capacitance larger than 1 pf is required for d1 and d2, both components should be placed between fb1 and fb2 and the headphone amplifier to minimize c shunt . place the chip as close as possible to the headpho ne connector to minimize antenna trace capacitance, cpcbant. keep the trace length short and narrow and as far above the reference plane as possible, restrict the trace to a microstrip topology (trace routes on the top or bottom pcb layers only), mi nimize trace vias, and relieve ground fill on the trace layer. note that minimizing capacitance has the effect of maximizing characteristic impedance. it is not ne cessary to design for 50 ? transmission lines. to reduce the level of digital noise passed to the antenna, rf shunt capacitors c5 and c6 may be placed on the left and right audio traces close to the headphone ampl ifier audio output pins. the recommended value is 100 pf or greater, however, the designer should confirm that the headphone amplifier is capable of driving the selected shunt capacitance. 3.5. headphone antenna design checklist ? select an antenna length of 1.1 to 1.45 m. ? select matching inductor l match to maximize signal strength across the fm band. ? select matching inductor l match with a q of 15 or greater at 100 mhz and minimal dc resistance. ? place inductor l match and headphone connector together and as far from potential noise sources as possible to reduce capacitive and inductive coupling. ? place the si47xx close to the headphone connector to mini mize antenna trace length. minimizing trace length reduces cp and the possibility for indu ctive and capacitive coupling into th e antenna by nois e sources. this recommendation must be followed for optimal device performance. ? select ferrite beads f1?f2 with 2.5 k ? or greater resistance at 100 mhz to maximize rshunt and, therefore, rp. ? place ferrite beads f1-f2 close to the headphone connector. ? select esd diodes d1-d3 with minimum capacitance. ? place esd diodes d1-d3 as close as possible to th e headphone connector for maximum effectiveness. ? place optional rf shunt capacitors near the headphone amp lifier?s left and right audio output pins to reduce the level of digital noise passed to the antenna.
an383 22 rev. 0.8 4. cable antenna for fm rece ive on fmi (si470x/2x/3x/8x only) the charger cable of a consumer product can be used as an fm antenna. this section describes how to interface the si47xx fmi input to a cable antenna. 4.1. cable antenna design figure 10. sample cigarette lighter adapter for cable antenna a typical cable antenna contains multiple inner wires/ conductors, which are covered with a protective ground shield. the coupling between the wires and the shield can cause the antenna to have large capacitance in the several hundred pico farad range. in order to boost the received fm voltage, it is necessary to minimize this capacitance. this reduction can be achieved by placi ng ferrite beads in series with each of the antenna?s conductors. 4.2. cable antenna schematic figure 11. cable antenna schematic ?
an383 rev. 0.8 23 to resonate the cable antenna within the fm band, the an tenna?s capacitance needs to be reduced. as described in section ?4.2. cable antenna schematic?, this reduction can be achieved by placing the ferrite beads in series with each of the antenna?s conductors. the capacitance s hould be further controlled by limiting the trace length from the cable ground shield and the rf input pin (fmi input) on the si47xx fm tuner. each of the components in the schematic above is explained in detail below: l1 (27 0nh) is the tuning inductor. this is the typical valu e used to resonate the cable antenna in the center of the fm band. f1 (2.5 k ? at 100 mhz) is a shunt ferrite to ground at the cable antenna side. a substantial amount of ground return current may flow through the cable antenna shield/ground because there are multiple conductors inside the cable along with power supply conductors . the ferrite will divert the ground re turn current of t he cable antenna to go through the shunt ferrite rather than going through the tuning inductor and/or si47xx chip. c1 (100 pf) is a dc blocking cap placed between the fmi pin and the cable antenna ground. the capacitor is used to isolate the cable return currents from the fmi pin. f2 (2.5 k ? at 100 mhz) is a series ferrite placed on the sign al conductor in the cable antenna. note that series ferrites should be placed on each signal conductor in the ca ble. the ferrite is used to isolate the signal conductors from the shield/ground of the cable antenna and reduce parasitic capacitance seen by the shield/ground. the choice of the ferrite is dependent upon the type of signal on each individual conductor. if the co nductor is used to carry power, then a ferrite wit h a large dc current carrying capability should be used. if the conductor is used to carry high frequency digital signals, make sure that th e ferrite does not block the high frequency component of these signals. likewise if the conductor is used to carry high frequency analog signals, make sure that the ferrite does not filter the high frequency. 4.3. cable antenna bill of materials the required bill of ma terials is shown below: table 13. bill of materials designator description notes l1 ind, 0603, sm, 270 nh, murata, lqw18anr27j00d c1 dc blocking capacitor, sm, 0402, x7r, 100 pf f1 shunt ferrite bead, ferritebead, sm, 0603, 470 ? , 1 a, murata, blm18pg471sn1j rated dc current > max expected ground return current f2 series ferrite bead, various types. recommended ferrite for power lines: ferritebead, sm, 0603, 470 ? , 1 a, murata, blm18pg471sn1j recommended ferrite fo r signals: ferritebead, sm, 0603, 2.5 k ? , 50 ma murata, blm18bd252dn1d for power signals, make sure the rated dc current > max expected ground return current. for all other signals, make sure ferrite does not block/filter the high frequency component of the signals.
an383 24 rev. 0.8 4.4. cable antenna layout place the chip as close to the cable antenna as possible. this will minimize the trace length going to the cable antenna which will minimize the parasitic capacitance. place the shunt ferrite for the grou nd return current as close to the cable as possible. putting the shun t ferrite for the ground return current close to the cable ensures that the ground return curr ent has minimal loop whic h will reduce noise coupling. the series ferrites also should be put as close as possible to the cable. this will minimi ze the parasitic capacitance seen by the fmi pin. 4.5. cable ante nna design checklist ? place the chip as close as possible to the ca ble antenna to minimize parasitic capacitance. ? place the tuning inductor, l1, as far away from noise sources as possible. ? make sure that the shunt ferrite has a dc rating that exceeds the expected max ground return current of the cable. ? place the shunt ferrite close to the cable. ? choose series ferrite that is appropriate for each type of signal in the conductor. ? place the series ferrite(s) close to the cable.
an383 rev. 0.8 25 5. embedded antenna for fm transmit on txo and receive on lpi (si4704/ 05/06/1x/2x only) the fm transmitter component on the si471x/2x and the fm receiver component on the si4704/05/06/2x support an embedded antenna interface through the txo/lpi pin. in the case of the si472x fm transceiver, the same embedded antenna can be used for both fm transmit and receive. 5.1. embedded antenna design an embedded antenna can be designed using a loose wire, fl ex circuit, or pcb trace and can be categorized into two types: stub antenna and loop antenna. for the purp ose of this application note, three types of embedded antenna will be covered in detail: ? embedded stub (wire) ? embedded loop (wire) ? embedded stub (pcb trace) the following table summarizes the advantages and disadvantages of these implementations. figure 12 is an example of a stub antenna in wire impl ementation buried inside a cellular handset. explanations of the dimensions a, b, c, and d ar e included later in this document. antenna description advantages disadvantages embedded stub (wire) ? wire attached to or molded inside product case ? connect to pin 4 for tx/ rx ? placement flexibility ? minimum pcb space ? easy to adjust length during design testing ? mechanical attachment to case required ? performance can be impacted by case shielding embedded loop (wire) ? wire loop attached to or molded inside product case ? connect to pin 4 for tx/ rx ? can achieve high efficiency per length ? placement flexibility ? minimum pcb space ? easy to adjust length during design testing ? mechanical attachment to case required ? performance can be impacted by case shielding embedded stub (pcb trace) ? wire trace fabricated on outer pcb copper layer ? connect to pin 4 for tx/ rx ? no mechanical attachment to case ? ease of product assembly ? pcb keep out regions required around antenna ? additional pcb space ? performance can be impacted by case shielding
an383 26 rev. 0.8 figure 12. stub antenna in wire implementation 5.1.1. embedded stub antenna?wire implementation a stub (wire) antenna is typically a float ing wire that is approximately 10 cm in length and is embedded inside the device with fm functionality. the antenna can be longer if the device's industrial design will accommodate it. the material for a stub (wire) antenna can be an actual wir e or a pcb trace. pcb traces can be either in flexible packaging (flexible pcb trace) or as a trace on the pcb. the 24awg wire has been experimentally proven to have optimal performance. the stub (wire) antenna should be placed such that it is not obstructed by a ground plane or shield. this requirement can be met by placing the antenna on an extr emity of the device (e.g., top or bottom) or on the perimeter. the antenna can also be embedded in the device plastic or outside the plastic with a protective covering. the flexible pcb antenna should be between a pcb and the device plastic such that the antenna trace is not obstructed by a ground plane or shield. the antenna is connected to pin 4 and resonated with the on-chip variable capacitor. 5.1.1.1. matching a 10 cm stub (wire) antenna has a capacitive impedance, typically more than 1~2 pf. the antenna is matched by resonating it with a shunt inductor and the on-chip shunt variable capacitor. see appendix b for inductor value calculation.
an383 rev. 0.8 27 5.1.1.2. configuration figure 13. stub (wire) antenna - side view figure 14. u-shaped stub (wire) antenna?orthogonal view 5.1.1.3. antenna layout guidelines ? route the antenna as a "u" shape as shown in figure 14. ?? a > 5 mm ?? b + c > 10 cm ? route the antenna as an "l" by removing segment d if a "u" is not possible. ? maximize antenna length (b+c >10 cm) to provide sufficient radiating power for transmit and maximize incident voltage for receive. ? keep the antenna as far from the ground plane, shield, an d other metal structures (e.g ., batteries) as possible (a > 5 mm), and make the enclosure from non-conductive material, such as plastic, to minimize parasitic capacitance and maximize radiation for transmit or maximize incident voltage for receive. ? antenna capacitance for an ideal wire antenna is approximated by cant = l/(198 x c), where l is length of wire in meters and c is speed of light (3.0 x 10 8 m/s). a general guideline to follow is to assume that each centimeter of wire antenna adds ~0.17 pf of capacitance (for l << ? /20).
an383 28 rev. 0.8 ? use an ideal vertical wire antenna as a reference point to measure the performanc e of the wire antenna. antenna capacitance will be larger and antenna performance will d egrade in a practical application where the wire antenna is bent parallel to the gnd plane. 5.1.2. embedded loop antenna?wire implementation a loop (wire) antenna is typically a floating wire that is approximately 13 cm or greater in circumference and is embedded inside the device with fm functionality. it is co nstructed with a floating wire or flexible pcb trace. the shape of the antenna can be circular or rectangular wit h the goal of maximizing the enclosed area. the 24awg has been experimentally proven to have optimal performa nce. a floating wire antenna is typically embedded in the plastics, or outside of the plastics ( with protective covering), at the perimeter of the de vice such that the antenna trace is not obstructed by the ground plane, shield, or other metal structures (e.g., batteries). placement of the flexible pcb is typically between the ma in pcb and plastics such that the antenna trace is not obstructed by a ground plane or shield. a loop antenna is si milar to a short wire antenna with the exception that the other end of the antenna is grounded. because the other en d is grounded, a loop antenna by itself is an inductor. 5.1.2.1. antenna matching a loop (wire) antenna is an inductor of high impedance . the antenna is matched by resonating it with a shunt inductor or capacitor and the on-chip shunt variable capacitor. 5.1.2.2. configuration figure 15. loop (wire) antenna?side view length (cm) c ant (pf) 10 1.68 11 1.85 12 2.02 13 2.19 14 2.36 15 2.53
an383 rev. 0.8 29 figure 16. rectangular loop (wire) antenna?orthogonal view 5.1.2.3. design guidelines ? route the antenna as shown in figure 16. ?? a > 5 mm ?? b + c + d + e > 13 cm ?? c > 3 cm ? maximize antenna length (b+c+d+e >13 cm) to provide su fficient radiating power fo r transmit and maximize incident voltage for receive. ? keep the antenna as far from the ground plane and sh ield as possible (a > 5 mm), and make the enclosure from non-conductive material (plastic), to minimize para sitic capacitance and maximize radiation for transmit or maximize incident vo ltage for receive. ? antenna inductance for an ideal loop antenna is given by l ant = n2 0 r[ln(8r/b)]. r: loop radius (m) n: number of turns 0 : permeability (4 ? x 10 ?7 n/a 2 ) b: wire radius (m) number of turns greater than one usually results in a hi gh inductance loop with which the varactor cannot resonate. it is acceptable to place two lo ops in a parallel structure to re duce the effective inductance. for a loop with a small radius used in cellular handset or mp3 applications, the loop antenna equation can be approximately applied to a rectangular loop of the same circumference. ? use an ideal vertical loop (wire) antenna as a reference point to measure the performance of the loop antenna. antenna performance will degrad e in a practical application where the lo op antenna is bent parallel to the gnd plane. radius (cm) turns total length (cm) l ant (nh) 21 12.6 111.5 31 18.8 182.6 41 25.1 257.9
an383 30 rev. 0.8 5.1.3. embedded stub antenna?pcb trace implementation (pin 4) a stub antenna (pcb trace) is constructed using a 10 cm or longer pcb trace. the material can be any standard pcb. the pcb trace must be ro uted in an area without any copper fill, such as grou nd or power pl anes or other traces. the antenna is connected to pin 4 a nd resonated with the on-chip variable capacitor. figure 17. stub (pcb trace) antenna?orthogonal view 5.1.3.1. antenna matching a 10 cm stub (wire) antenna is capaciti ve, typically more than 1~2 pf. the ant enna is matched by resonating it with a shunt inductor and the on-chip shunt variable capacito r. see appendix a and appendix b for inductor value calculation. 5.1.3.2. configuration figure 18. stub (pcb trace) antenna?side view 5.1.3.3. design guidelines ? route the antenna as a "u" shape as shown in figure 7. ?? a > 5 mm ?? b + c > 10 cm ? route the antenna as an "l" by removing segment d if a "u" is not possible. ? maximize antenna length (b + c >10 cm) to provide su fficient radiating power for transmit and maximize incident voltage for receive. ? it is not important to match d = b. ? keep the antenna as far from the ground plane and sh ield as possible (a > 5 mm), and make the enclosure from non-conductive material (plastic), to minimize para sitic capacitance and maximize radiation for transmit or maximize incident vo ltage for receive. ? antenna capacitance for an ideal pcb trace antenna is gi ven by cant = l/(198 x c), where l is length of wire in meters and c is speed of light (3.0 x 10 8 m/s). a general guideline to follow is to assume that each centimeter of wire antenna adds ~0.17 pf of capacitance (for l << ? /20).
an383 rev. 0.8 31 5.2. embedded antenna schematic figure 19 shows the embedded antenna schematic. figure 19. embedded antenna schematic l1 is the tuning inductor and typical value is 120nh. l1 needs to be chosen such that the resonant circuit of l1 and the total capacitance at the txo/lpi pin will resonate at the fm band (76-108mhz). th e total capacitance at the txo/lpi pin includes the internal on-chip varactor, the an tenna and all of the parasitic capacitance at that node. therefore it is important to check the readantcap va lue as described below when the product is in fully assembled configuration. there are two steps to select the value of l1: calculate l1 using the formula below, and then monitor the on-chip varactor value readantcap by sending the tx_tun e_status or fm_tune_status command to make sure the on-chip varactor is still in-range. the first step is approximating the value of l1 (which ca n be skipped). the formula to calculate l1 is as follows: where: f = frequency of fm band ctotal = total capacitance at the txo/lpi pin note that ctotal will vary because of the automatic tuning of th e internal on-chip varact or. the internal on-chip varactor has value from 1-191 for 0.25pf step which equals to 0.25pf to 47.75pf. knowing the other capacitance at the txo/lpi pin which is layout and component depende nt will give a range of ctotal. after the approximate ctotal has been calculated, l1 can be chosen to satisfy the formula above for the fm band. length (cm) c ant (pf) 10 1.68 11 1.85 12 2.02 13 2.19 14 2.36 15 2.53 l1 1 2 ? f ?? 2 ctotal ------------------ -------------- =
an383 32 rev. 0.8 after choosing the right l1 value, the user is still required to check th e on-chip varactor value readantcap by sending the tx_tune_status or fm_tune_status command to make sure that the on-chip varactor has not gone out-of-range. user also can jump to this second st ep right away and skip the first step of approximating l1 by trying different values of l1. the procedure to monitor the readantcap is as follows: ? select at least three frequencies in the bottom, middle and top of the fm band (e.g. 88, 98, and 108 mhz) and get the readan tcap values. ? it is even better if user sweeps the ent ire fm band and gets the readantcap values. ? l1 has a correct inductance value if ?? 1 < readantcap < 191 ?? readantcap at 88 mhz > readantcap at 98 mhz > readantcap at 108 mhz ?? be suspicious when readantcap returns the middle value of 97. it may be an indication that the inductor value is not correct. ? l1 is not the right value and needs to be changed if either one of these three conditions occur: ?? readantcap returns the bottom valu e of 1: it indicates that there is too mu ch capacitance at the txo/lpi pin. l1 needs to be adjusted to a smaller value or the better solution is to try to reduce the parasitic capacitance at the txo/lpi pin ?? readantcap returns a middle value of 97: it indicates that t here is way too much capacitance at the txo/lpi pin. l1 needs to be adjusted to a smaller value or the better solution is to try to reduce the parasi tic capacitance at the txo/lpi pin ?? readantcap returns the top value of 191: it indicates that there is too little of a capacitance at the txo/lpi pin (unlikely to happen). l1 needs to be adjusted to a bigger value. the rest of the components in the embedded antenna schematic are optional. d1 is the esd diode and it is only necessary when there is an exposed pad going to the txo/lpi pin. r1 is the esd current limiting resist or and used in conjunction with d1. it is only necessary when there is an exposed pad going to the txo/lpi pin. note: when using an electrically short monopole antenna for trans mit, the radiated power varies with frequency. specifically, as the transmit frequency increases, the monopole anten na becomes more efficient and hence the radiated power increases. this is important when testing for fcc limit becaus e the transmit power level of the chip needs to be adjusted across the fm band. 5.3. embedded antenna bill of materials table 14. embedded antenna bill of materials designator description note l1 tuning inductor (typically 120 nh) r1 current limiting resistor for esd, 2 ? optional, only needed if there is any exposed pad going to the txo/lpi pin. d1 esd diode optional, only needed if there is any exposed pad going to the txo/lpi pin.
an383 rev. 0.8 33 5.4. embedded antenna layout the placement of the chip going into the embedded antenna is critical. place the chip as close as possible to the embedded antenna feedline. this will minimize the trace going to the embedded antenna wh ich in turn will minimize parasitic capacitance. if long trace is need ed between the txo/lpi pin to the embedded antenna, keep the trace as a microstrip topology where the trace is on the top or bottom layer. do not bury the trace on the inner layer. relieve the ground fill along the trace which includes the ground fill on th e inner layer. note that the goal is to minimize the parasitic capacitance as much as possible, it is not necessary to design a 50 ? transmission lines in this applications because the embedded antenna is a high impedance ante nna, and the parallel resonant circuit is also high impedance at the resonant frequency. put the optional esd diode d1 and esd current limiting resistor r1 as close to the embedded antenna as possible to ensure optimal esd performance. 5.5. embedded antenna design checklist ? place the chip as close as possible to the embedded ant enna feedline to minimize parasitic capacitance. ? select tuning inductor l1 with a q>30 to maximize radiated power and received voltage. ? select tuning inductor l1 as large as possible to maximize radiated power and incident voltage. ? place the antenna, and in particular the end of the anten na opposite the si47xx as fa r from the ground plane as possible to maximize radiated and received power. ? place inductor l1 and the si47xx chip as far from potential noise sources as possible to reduce capacitive and inductive coupling. ? place optional components l2 to filter vco spurs if needed. ? place optional components d1 and r1 to achieve 8 kv cont act discharge esd protection if the antenna is exposed. ? select esd diode d1 with minimum capacitance.
an383 34 rev. 0.8 6. cable antenna for fm transm it on txo and receive on lpi (si4704/05/06/1x/2x only) this section describes how to interface the si47xx txo ou tput and lpi input to a cable antenna. an example of a cable antenna would be a cigarette light adapter (cla) ca ble or a bundled cable going to the consumer product that may contain power conductors , audio signals, control signals, or any other auxiliary signals. 6.1. cable antenna design using a cable as the antenna for fm usua lly means that the signal has to be driven to and/or received from the cable shield or ground . this is because most cable will have a protecti ve shield covering th e inner wires. in this case, the capacitive coupling between the ground shield and all other conductors can be very large. as a comparison, capacitance of a three-conductor headph one cable is approximately 10?20 pf because headphone cable does not have ground shield and only has two conductors plus a ground conductor. however, the capacitance from a cable antenna can be greater than 100?200 pf because of the ground shield and multiple conductors. this antenna capacitance can be reduced by pl acing ferrite beads on all conductor traces as shown in figure 21. minimizing an tenna capacitance will maximize tr ansmit and receive voltage. the following picture shows a cigarette light adapter (cla ) cable that can be used as a cable antenna for fm. figure 20. cigarette lighter adapter (cla) 6.2. cable antenna schematic figure 21. cable antenna schematic l1 (12 0nh) is the tuning inductor for the transmitter and receiver and the return curren t path for transmitter. the on-chip varactor can be configured to automatically re sonate with the tuning inductor. because of the large capacitance, it is also generally hard to have a high-q system with a cable antenna. a high-q system is generally desirable when using short antenna to maximize transmit and receive voltage. fortunately, a high-q system may not be necessary for a cable antenna since the cabl e antenna is an efficient radiator and receiver. f1 (2.5 k ? at 100 mhz) is a shunt ferrite to ground at the cable antenna side. a substantial amount of ground return current may flow through the cable antenna shield/ground because there are multiple conductors inside the cable along with power supply conductors . the ferrite will divert the ground re turn current of t he cable antenna to go through the shunt ferrite rather than going through the tuning inductor and/or si47xx chip.
an383 rev. 0.8 35 the important property of the shunt ferr ite is its dc current ca rrying capability and this depends on what is the maximum current that the cable antenna can deliver. for example if the cable antenna can charge the accessory connected to it with a 1 a of current, then the shunt ferrite should have a dc current rating of greater than 1 a (e.g., 3a). c1 (100 pf) is a dc blocking cap placed between the tx o/lpi pin and the cable antenna ground. the capacitor is used to isolate the cable return currents from the txo/lpi pin. f2 (2.5 k ? at 100 mhz) is a series ferrite placed on the sign al conductor in the cable antenna. note that series ferrites should be placed on each signal conductor in the ca ble. the ferrite is used to isolate the signal conductors from the shield/ground of the cable antenna and reduces parasitic capacitance seen by the shield/ground. the choice of the ferrite is dependent upon the type of signal on each individual conductor. if the co nductor is used to carry power, then a ferrite wit h a large dc current carrying capability should be used. if the conductor is used to carry high frequency digital signals, make sure that th e ferrite does not block the high frequency component of these signals. likewise if the conductor is used to carry high frequency analog signals, make sure that the ferrite does not filter the high frequency. 6.3. cable antenna bill of materials the required bill of ma terials for the figure 21 is shown in table 15. table 15. cable antenna bill of materials designator description notes l1 tuning inductor, ind, 0603, sm, 120 nh, murata, lqw18anr12j00d, q>35 c1 dc blocking capacitor, sm, 0402, x7r, 100 pf f1 shunt ferrite bead, ferritebead, sm, 0603, 470 ? , 1 a, murata, blm18pg471sn1j rated dc current > max expected ground return current f2 series ferrite bead, various types. recommended ferrite for power lines: ferritebead, sm, 0603, 470 ? , 1 a, murata, blm18pg471sn1j recommended ferrite for signa ls: ferritebead, sm, 0603, 2.5 k ? , 50 ma murata, blm18bd252dn1d for power signals, make sure the rated dc current > max expected ground return current. for all other signals, make sure ferrite does not block/filter the high frequency component of the signals.
an383 36 rev. 0.8 6.4. cable antenna layout place the chip as close to the cable antenna as possible. this will minimize the trace length going to the cable antenna which will minimize the parasitic capacitance. place the shunt ferrite for the ground return current as cl ose to the cable as possible . putting the shunt ferrite for the ground return current cl ose to the cable ensures t hat the ground return curren t has minimal loop which will reduce noise coupling. the series ferrites also should be put as cl ose as possible to the cable. this will minimize the parasitic capacitance seen by the txo/lpi pin. 6.5. cable ante nna design checklist ? place the chip as close as possible to the cabl e antenna to minimize parasitic capacitance. ? place the tuning inductor, l1, as far away from the noise source as possible. ? make sure that the shunt ferrite has a dc rating that e xceeds the expected max ground return current of the cable. ? place the shunt ferrite close to the cable. ? choose series ferrite that is appropriate for each type of signal in the conductor. ? place the series ferrite(s) close to the cable.
an383 rev. 0.8 37 7. whip antenna for fm/wb re ceiver on fmi (s i4707/3x only) a whip antenna is a typical monopole antenna, which is us ed in portable weather band receivers. it can also be used for sw applications. for additional details, see "10. whip antenna for sw receiv e on ami (si4734/35 only)" on page 45. 7.1. fm/wb whip antenna design a whip antenna is a monopole antenna with a stiff but flex ible wire mounted ve rtically with one end adjacent to the ground plane. there are various types of whip anten na including long non-telescopic metal whip antenna, telescopic metal whip antenna, and rubber whip antenna. figure 22 shows the telescopic whip antenna. figure 22. telescopic whip antennas the whip antenna is capacitive, and its output capaci tance depends on the length of the antenna (maximum length ~56 cm). at 56 cm length, the capacitance of the whip ant enna ranges from 18 pf to 32 pf for the us fm band. the antenna capacitance is about 22 pf in the center of the us fm band (98 mhz). 7.2. fm/wb whip antenna schematic figure 23. fm/wb whip antenna l1 (56nh) is the matching inductor and it combines with the antenna impedance and the fmi impedance to resonate in the fm band. c5 (1nf) is the ac coupling cap going to the fmi pin. u3 is a required esd diode since the antenna is expos ed. the diode should be chosen with no more than 1pf parasitic capacitance, such as t he california micro device cm1213.
an383 38 rev. 0.8 7.3. fm/wb whip ante nna bill of materials 7.4. fm/wb whip antenna layout place the chip as close as possible to the whip antenna. this will minimize the trace le ngth between the device and whip antenna which in turn will minimize parasitic capacitance and th e possibility of noise co upling. place inductor l1 and the antenna connector together and as far from po tential noise sources as possible and away from the i/o signals of the si4736/37/38/39 . place the ac coupling capacitor, c5, as close to the fmi pin as possible. place esd diode u3 as close as possible to the whip an tenna input connector for maximum effectiveness. 7.5. fm/wb whip antenna design checklist ? maximize whip antenna length for optimal performance. ? select matching inductor l1 with a q of 15 or greater at 100mhz and minimal dc resistance. ? select l1 inductor value to maximize resonance gain from fm frequency (88 mhz) to wb frequency (~162 mhz) ? place l1 and whip antenna close together and as far from potential noise sources as possible to reduce capacitive and inductive coupling. ? place the chip as close as possible to the whip ante nna to minimize the antenna trace length. this reduces parasitic capacitance and hence redu ces coupling into the antenna by noise sources. this recommendation must be followed for optimal device performance. ? place esd u3 as close as possible to the whip antenna for maximum effectiveness. ? select esd diode u3 with minimum capacitance. ? place the ac coupling capacitor, c5, as close to the fmi pin as possible. table 16. fm/wb whip antenna bill of materials designator description wip_antenna whip antenna l1 tuning inductor, 0603, sm, 56 nh, murata, lqw18an56nj00d c5 ac coupling capacitor, 1nf, 10%, cog u3 ic, sm, esd diod e, sot23-3, cali- fornia micro devices, cm1213-01st
an383 rev. 0.8 39 8. ferrite loop antenna for am/lw r eceive on ami (si 4730/31/34/35/36/37 only) there are two types of antenna that will work well for an am receiver: a ferrit e loop antenna or an air loop antenna. a ferrite loop antenna can be placed internally on the de vice or externally to the device with a wire connection. when the ferrite loop antenna is placed internally on th e device, it is more suscep tible to picking up any noise within the device. when the ferrite loop antenna is placed outside a device, e.g., at the end of an extension cable, it is less prone to device noise activity and may result in better am reception. 8.1. ferrite loop antenna design figure 24 shows an example of ferrite loop antennas. the le ft figure is the standard size ferrite loop antenna. it is usually used in products with a lot of space, such as deskt op radios. the right figure is the miniature size of the loop antenna. it is usually used in small products where space is at a premium, such as cell phones. if possible, use the standard size ferrite loop antenna as it has a better sensitivity than the miniature one. figure 24. standard and miniature ferrite loop antennas a loop antenna with a ferrite inside should be designed such that the inductance of the ferrite loop is between 180 and 450 h for the si473x am receiver. table 17 lists the recommended ferrite loop antenna for the si473x am receiver. the following is the vendor information for the ferrite loop antennas: guangzhou jiaxin electronics shenzhen sales office email:sales@firstantenna.com web:www.firstantenna.com table 17. recommended ferrite loop antenna part # diameter length turns ui type application sl8x50mw70t 8 mm 50 mm 70 400 mn-zn desktop radios sl4x30mw100t 4 mm 30 mm 100 300 ni-zn portable radios (mp3, cell, gps, ?) sl3x30mw105t 3 mm 30 mm 105 300 ni-zn sl3x25mw100t 3 mm 25 mm 110 300 ni-an sl5x7x100mw70t 5 x 7 mm 100 mm 70 400 mn-zn desktop radios
an383 40 rev. 0.8 8.2. ferrite loop antenna schematic figure 25. am ferrite loop antenna schematic c1 is the ac coupling cap going to the ami pin and its value should be 0.47 f. d1 is an optional esd diode if there is an exposed pad going to the ami pin. 8.3. ferrite loop antenna bill of materials table 18. ferrite loop antenna bill of materials designator description note ant1 ferrite loop antenna, 180?450 h c1 ac coupling capacitor, 0.47 f, 10%, z5u/x7r d1 esd diode, ic, sm, sot23-3, california micro devices, cm1213-01st optional; only needed if the there is any exposed pad going to the ami pin.
an383 rev. 0.8 41 8.4. ferrite loop antenna layout place the chip as close as possible to the ferrite loop ant enna feedline. this will minimize the trace going to the ferrite antenna which in turn will mini mize parasitic capacitance, and also will minimize the possibility of noise sources coupling to the trace. the placement of the am antenna is critical, since am is susceptible to noise sources causing interference in the am band. noise sources can come from clock signals, sw itching power supply, and digital activities (e.g., mcu). when the am input is interfaced to a ferrite loop stick antenna, the placement of the ferrite loop stick antenna is critical to minimize inductive coupling. place the ferrite loop stick antenna as far away from interference sources as possible. in particular, make sure th e ferrite loop stick antenn a is away from signals on the pcb and away from even the i/o signals of the si473x. do not route any signal under or near the ferrite loop stick. route digital traces in between ground plane for best performance. if that is no t possible, route digital traces on the opposite side of the chip. this will minimize capacitive coup ling between the plane (s) and the antenna. to tune correctly, the total capacitance seen at the ami input needs to be minimized and kept under a certain value. the total acceptable capacitance depends on the induct ance seen by the si4730/31 at its am input. the acceptable capacitance at the am input can be calculated using the formula shown in equation 2. equation 2. expected total capacitance at ami where: c to ta l = total capacitance at the ami input l effective = effective inductance at the ami input f max = highest frequency in am band the total allowable capacitance, when in terfacing a ferrite loop stick antenna, is the effective capacitance resulting from the ami input pin, the capacitance from the pcb, and the capacitance from the ferrite loop stick antenna. the inductance seen at the ami in this ca se is primarily the inductance of the ferrite loop stick antenna. the total allowable capacitance in the case of an air loop antenna is the effective capacitance resulting from the ami input pin, the capacitance of the pcb, the capacitance of the transformer, and the capacitance of the air loop antenna. the inductance in this case should also take all the elem ents of the circuit into account. the input capacitance of the ami input is 8 pf. the formula shown in equation 2 gives a total capacitance of 29 pf when a 300 h ferrite loop stick antenna is used for an am band with 10 khz spacing, where the highest frequency in the band is 1710 khz. 8.5. ferrite loop an tenna design checklist ? place the chip as close as possible to the ferrite loop ant enna feedline to minimize parasitic capacitance and the possibility of noise coupling. ? place the ferrite loop stick antenna away from any source s of interference and even away from the i/o signals of the si473x. please make sure that the am antenna is as far away as possible from circuits that switch at a rate which falls in the am band (520?1720 khz). ? place optional component d1 if the antenna is exposed. ? select esd diode d1 with minimum capacitance. ? do not place any ground plane under the ferrite loop stick an tenna if the ferrite loop stick antenna is mounted on the pcb. the recommended ground separation is 1/4 inch or the width of the ferrite. ? route traces from the ferrite loop stick connectors to th e ami input via the ac coupling cap c1 such that the capacitance from the traces and the pads is minimized. c total 1 2 ? f max ?? 2 l effective ---------------- ----------------- --------------- =
an383 42 rev. 0.8 9. air loop antenna for am/lw recei ve on ami (si4730/31/34/35/36/37 only) an air loop antenna is an external am antenna (bec ause of its large size) typically found on home audio equipment. an air loop antenna is placed external to the product enclosure maki ng it more immune to system noise sources. it also will have a better sensitivity compared to a ferrite loop antenna. 9.1. air loop antenna design figure 26 shows an example of an air loop antenna. figure 26. air loop antenna unlike a ferrite loop, an air loop ante nna will have a smaller equiva lent inductance because of the absence of ferrite material. a typical inductance is on the order of 10 to 20 h. therefore, in order to interface with the air loop antenna properly, a transformer is required to raise the inductance into the 180 to 450 h range. t1 is the transformer to raise the inductance to within 18 0 to 450 h range. a simple fo rmula to use is as follows: typically a transformer with a turn rati o of 1:5 to 1:7 is good for an air lo op antenna of 10?20 h to bring the inductance within the 180 to 450uh range. choose a high-q transformer with a coupling coefficient as close to 1 as possible and use a multiple strands litz wire for the transformer winding to reduce the skin effect. all of this will ensure that the transformer will be a low loss transformer. finally consider using a shielded enclosure to house the transformer or using a torroidal shape core to prevent noise pickup from interfering sources. a few recommended transformers are listed in table 19. table 19. recommended transformers transformer 1 transfo rmer 2 transformer 3 vendor jiaxin dianzi umec umec part number sl9x5x4mwtf1 tg-utb01527s tg-utb01526 type surface mount surface mount through hole primary coil turns (l1) 12t 10t 10t secondary coil turns (l2) 70t 55t 58t wire gauge ulsa / 0.07mm x 3 n/a n/a inductance (l2) 380h 10% @ 796khz 184h min, 245h typ @ 100 khz 179 h min, 263 h typ @ 100 khz q 130 50 75 l equivalent n 2 l airloop =
an383 rev. 0.8 43 the following is the vendor information for the above transformer: vendor #1: jiaxin dianzi guangzhou jiaxin electronics shenzhen sales office email: sales@firstantenna.com web: www.firstantenna.com vendor #2: umec usa, inc. website: www.umec-usa.com www.umec.com.tw 9.2. air loop antenna schematic figure 27. am air loop antenna schematic c1 is the ac coupling cap going to the ami pin and its value should be 0.47 f. d1 is a required esd diode since the antenna is exposed.
an383 44 rev. 0.8 9.3. air loop antenna bill of materials 9.4. air loop antenna layout place the chip and the transf ormer as close as possible to the air loop antenna feedline. th is will minimize the trace going to the air loop antenna which in turn will minimize parasiti c capacitance and the possibility of noise coupling. when an air loop antenna with a tran sformer is used with the si 473x, minimize inductive coupling by making sure that the transformer is placed away from all sources of in terference. keep the transformer away from signals on the pcb and away from even the i/o signals of the si473x. do not route any si gnals under or near the transformer. use a shielded transformer if possible. 9.5. air loop antenna design checklist ? select a shielded transformer or a torroidal shape transformer to prevent noise pickup from interfering sources ? select a high-q transformer with coupling coef ficient as close to 1 as possible ? use multiple strands litz wir e for the transformer winding ? place the transformer away from any sources of interference and even away from the i/o signals of the si473x. please make sure that the am antenna is as far away as po ssible from circuits that switch at a rate which falls in the am band (520?1720 khz). ? route traces from the transformer to the ami input via th e ac coupling cap c1 such that the capacitance from the traces and the pads is minimized. ? select esd diode d1 with minimum capacitance. table 20. air loop antenna bill of materials designator description note loop_antenna air loop antenna t1 transformer, 1:6 turns ratio c1 ac coupling capacitor, 0.47 f, 10%, z5u/x7r d1 esd diode, ic, sm, sot23-3, california micro devices, cm1213-01st
an383 rev. 0.8 45 10. whip antenna for sw re ceive on ami (si4734/35 only) the whip antenna is a typical monopole antenna used in portable sw receivers. additionally, it can be used for fm applications as covered in se ction 6. this whip antenna sch ematic in this section will in clude the circuit for fm and ferrite loop antenna for am. in-depth analysis of the whip antenna for fm is covered in section 6, while in-depth analysis for the am ferrite loop antenna is covered in section 7. 10.1. sw whip antenna design the whip antenna is a monopole antenna with a stiff but fl exible wire mounted vertically with one end adjacent to the ground plane. the whip antenna is capacitive and its output capacitance depends on the length of the antenna (maximum length ~56 cm). at 56 cm length , the capacitance of the whip antenna is about 12 pf at sw frequencies and approximately 22 pf at the center of the fm band. there are various types of whip antennas including the l ong non-telescopic metal whip antenna, telescopic metal whip antenna, and rubber whip antenna. the following fi gure shows the rubber and the telescopic whip antenna. figure 28. telescopic whip antenna
an383 46 rev. 0.8 10.2. sw whip antenna schematic the following figure shows the sw whip antenna schemat ic along with the fm whip antenna interface and am ferrite loop antenna interface. figure 29. whip antenna schematic plus fm circuit and am ferrite antenna l1 (4.7 h) is an inductor, which together with the si4734 /35 varactor (varactor set to 1) acts as a low-pass filter with peaking in the sw band. this inductor value is chosen assuming 12 pf capacitance of the whip antenna, 18 pf ac coupling cap (c1) to fmi, 7 pf ami input capacitance (cami) and 8 pf parasitic capacitance on the board (cpar). if either of these values changes, the inducto r has to be tweaked to achieve peaking in the sw band (desired peaking at 23 mhz). the equiva lent schematic model is shown below:
an383 rev. 0.8 47 figure 30. sw whip antenna equivalent model ferrite_antenna is a ferrite loop antenna that has a dual purpose. in sw application, the ferrite_antenna serves as an inductor to ground, while in am application it serves as an antenna. ferrite_antenna can be replaced with a 220 h real inductor if am is not used. c8 (0.47 f) is the ac coupling cap going to the ami pin. u2 and u3 are required esd diodes since the antenna is exposed. the diodes should be chosen with no more than 1 pf parasitic capacitance, such as the california micro device cm12 13. (u3 needs to be considered for fm application only) c3 (33 pf) is a capacitor, which toge ther with the ferrite antenna (or a 220 h shunt inductor) provides a trap for the am frequencies. center frequency of the trap is calculated using the following equation: c1 (18 pf) is the ac coupling cap going to fmi pin (optional?for fm application only) l2 (180 nh) is the tuning inductor for fm (optional?for fm application only). this in ductor together with the whip antenna capacitance (~22 pf at the center of fm band) , 18 pf ac coupling cap (c1) and 5 pf typical fmi input capacitance (cfmi) resonates in the fm band. if either of the capacitance values changes, the inductor has to be tweaked to achieve peaking in the fm band (desired pea king at 100 mhz). the equiva lent schematic to model is shown below: figure 31. fm whip antenna schematic model when switch sw1 is on the other posit ion (pin 2 connected to pin 3), the whip antenna is disconnected and the ferrite acts as an antenna for am. go to section 7 for in-depth analysis of am ferrite loop antenna. f ctrap 1 2 ? c3 l ferrite ? ?? ? ? ------------------------------------------------------------------- - =
an383 48 rev. 0.8 10.3. sw whip antenn a bill of materials designator description notes wip_antenna whip antenna l1 low pass filter inductor, 1008, sm, 4.7 h, coilcraft, 1008cs-472glb q of 20 or greater at 25 mhz and minimal dc resistance. sw1 spdt switch optional, only needed if the design requires switching between am and sw. not required for sw only applications. c3 capacitor, 33 pf, 5%, cog c8 ac coupling capacitor, 0.47 f, 10%, z5u/x7r ferrite_antenna am antenna optional, can be replaced with a 220 h shunt inductor for sw only applications u2, u3 ic, sm, esd diode, sot23-3, california micro devices, cm1213-01st c1 capacitor, 18 pf, 5%, cog optional, only for fm l2 ind, 0603, sm, 180 nh, murata, lqw18anr18j00d optional, only for fm
an383 rev. 0.8 49 10.4. sw whip antenna layout place the chip as close as possible to the whip antenna. this will minimize the trace length between the device and whip antenna which in turn will minimize parasitic capacitance and the possibilit y of noise coupling. place the whip antenna away from any sources of interference and away from the i/o signals of the si4734/35. place the ac coupling capacitor, c8, as close to the ami pin as possi ble. place the ac coupling capacitor, c1, as close as possible to the fmi pin. place esd diodes u2 and u3 as close as possible to the whip antenna input connector for maximum effectiveness. 10.5. sw whip an tenna design checklist ? maximize whip antenna length for optimal performance. ? select matching inductor l1 with a q of 20 or greater at 25 mhz and minimal dc resistance. ? select l1 inductor value to maximize signal strength across the fm band. ? place l1 and whip antenna close together and as far from potential noise sources as possible to reduce capacitive and inductive coupling. ? place the chip as close as possible to the whip ante nna to minimize the antenna trace length. this reduces parasitic capacitance and hence redu ces coupling into the antenna by noise sources. this recommendation must be followed for optimal device performance. ? place esd diodes u2 and u3 as close as possible to the whip antenna for maximum effectiveness. ? select esd diodes u2 and u3 with minimum capacitance. ? place the ac coupling capacitor, c8, as close to the ami pin as possible. ? follow the design checklist in "8. ferrite loop antenna for am/lw receive on ami (si4730/31/34/35/36/37 only)" on page 39 for the ferrite antenna to optimize am performance (if am is used in addition to sw).
an383 50 rev. 0.8 a ppendix a?fm r eceive h eadphone a ntenna i nterface m odel the simplified circuit model for the headphone antenna interface shown in figure 32, ?headphone antenna and matching network model?, and includes the headphone ante nna, matching inductor, pcb and SI4700/01 lna. this section discusses maximizing voltage gain across the fm band at the lna input by varying headphone antenna and pcb parameters, and selecting the optimal matching indu ctor. it is very important to note that the performance is optimized by maximizing input voltage, not power. figure 32. headphone antenna and matching network model r ant antenna resistance c ant antenna capacitance l match inductance match c pcbant pcb antenna trace capacitance r shunt shunt resistance of ferrites c shunt audio conductor shunt capacitance c lna lna capacitance r lna lna resistance the headphone antenna and matching network model can be further simplified and represented in the form of a parallel resonant rlc circuit as shown in figure 33, ?para llel resonant rlc circuit mode l?. in this si mplified model the parallel resistance, r p , represents the antenna resistance, r ant , the shunt resistance of ferrites on the left and right audio conductors, r shunt , and the lna resistance, r lna . the parallel capacitance, c p , represents the antenna capacitance, c ant , pcb antenna trace capacitance, c pcbant , audio conductor shunt capacitance, c shunt , and lna capacitance, c lna . l match r ant c pcbant r shunt c lna r lna headphone antenna pcb fm receive lna c shunt c ant match
an383 rev. 0.8 51 figure 33. parallel resonant rlc circuit model c p = parallel capacitance r p = parallel resistance l match = inductance match l match is required to prevent the antenna from being shorted to ground at rf frequencies and to provide a path to ground at audio frequencies for return current from the headphone amplifier. selecting the proper value of l match will maximize voltage gain across the fm band for optimal rf performance. to maximize voltage gain across the fm band: 1. the value of r p should be maximized to maximize the voltage at the lna input. 2. the q of the circuit should be minimized to maintain a flat response across the fm band. 3. the value of l match should be chosen such that the circuit resonates in the center of the fm band. the value of r p should be maximized to maximize the voltage at the lna input. the parallel resistance, r p , shown in figure 33, ?parallel resonant rlc circuit model? is defined as: the lna resistance, r lna , will range from 4 to 6 k ? during normal operation. the shunt resistance, r shunt , is the parallel addition of ferrite resistance on the left and right audio conductors, and other conductors for microphone audio, switching or other circuits, if applicable. r shunt should be as large as possible to maximize rp. specific recommendations for ferrite values can be found in sect ion "3.2. headphone antenna schematic" on page 19. the antenna source resistance, r ant , will range from approximately 500 ? for shorter antennas to several thousand ohms for longer antennas. r ant * is the parallel circuit model for r ant near the resonant frequency, f, of the rlc circuit, and is approximated as: the antenna length should be 1.1 to 1.45 m, wit h optimal performance at 1.45 m to maximize r ant *. the q of the parallel resonant rlc circ uit shown in figure 33, ?parallel reson ant rlc circuit model? is defined as: l match c p r p match antenna,pcb & lna r p r lna r shunt r ant * ?? ?? = r ant *r ant q ant 2 1 + ?? ? r ant 1 2 ? fr ant c ant -------------------- ----------------- ?? ?? 2 1 + ?? ?? = q p r p l p c p ------- ----------- - =
an383 52 rev. 0.8 the q of the circuit should be minimized to maintain a fl at response across the fm band. to minimize the q of the circuit with a parallel resistance, r p , that is maximized, the parallel capacitance, c p , should be minimized and l match should be maximized. the parallel capacitance, c p , shown in figure 33, ?parallel resonant rl c circuit model? is defined as follows: the pcb antenna trace capacitance, c pcbant , is determined by the structure of the trace and is typically 3 to 4 pf per inch as a rule of thumb. the audio conductor shunt capacitance, c shunt , is the parallel addition of pcb trace and component capacitance with respect to ground on th e left and right audio conductors, and other conductors such as the microphone and switch if applicable. both c pcbant and c shunt should be as small as possible to minimize c p . specific schematic and layout recommendations minimizing c shunt can be found in section "3.2. headphone antenna schematic" on page 19 and section "3.4. headphone antenna layout" on page 21. specific layout recommendation for minimizing c pcbant can be found in section ?3.4. headphone antenna layout?. the lna capacitance, c lna , will range from 4 to 6 pf during normal operation. the ant enna capacitance, c ant , will range from zero to several picofarads, depending on antenna length. c ant * is the parallel circuit model of c ant near the resonant frequency, f, of the rl c circuit, and is approximated as follows: for a given value of parallel capacitance c p , the inductor value l match should be chosen such that the circuit resonates at the center of the fm band. the resonant frequency, f, of the parallel rlc circuit shown in figure 33, ?parallel resonant rlc circuit model? is defined as follows: normally it is difficult to reliably measure all of the impedances required to calculate an optimal value for l match . an easier approach is to measure the syste m performance with different values of l match and choose the best values based on these measurements. typical l match values range from 100 to 400 nh. there are two test methods available for selecting the correct value of l match to properly tune the headphone antenna interface circuit. both methods require injecting a test signal from a signal generator into the network through a source resistance, r test , and adjusting the matching inductor, l match , to maximize the voltage at the lna input at several points across the fm band. r test should be 20 k ? or larger to prevent loading of the resonant antenna circuit. figure 34, ?parallel resonant rl c circuit model test circuit ? shows the parallel resonant rlc model test circuit required for both test methods. c p c pcbant c shunt c lna c ant * ?? ?? ?? = c ant *c ant q ant 2 q ant 2 1 + --------------- ----------- ?? ?? ?? c ant ,for q 1 ? ?? ? l match c p ? --------------- -------------- -------------- - =
an383 rev. 0.8 53 figure 34. parallel resonant rlc circuit model test circuit the first test method requires reading the received signa l strength (rssi) measured by the fm receiver and the second method requires probing the lna input with a low-capacitance fet probe and spectrum analyzer. the advantage of the rssi method is that no external meas urement equipment is required; however, a provision must be made for reading rssi from the device. the advantage of the fet probe method is that reading the rssi from the fm receiver is not necessary, and measurement accuracy by using a spectrum analyzer and probe will be improved; however, excess capacitive loading of the fet probe may affect the measurement results. care should be taken to select a probe with minimum capacitance when using this approach. figure 35, ?headphone antenna example test signal injection frequency response? sh ows the frequency response for four values of l match using the rssi tuning method. l match c p r p match antenna,pcb & lna r test test
an383 54 rev. 0.8 figure 35. headphone antenna example test signal injection frequency response it is clear from figure 35, ?headphone antenna example test signal injection frequ ency response? that the matching inductor, lmatch, is preferred to no matching inductor, however, selecting the best value for lmatch can be difficult by inspection. select the optimal value for lmat ch by following these guidelines: 1. the mean value of rssi should be maximized. 2. the standard deviation of rssi should be minimized. table 21 shows 270 nh is the optimal choice for lmatch because it maximizes the mean rssi and minimizes the rssi standard deviation. table 21. headphone antenna example test signal injection mean and standard deviation 200 nh 270 nh 390 nh mean (db) 31.5 32.4 32.1 standard deviation (db) 3.0 1.7 1.9 15 20 25 30 35 40 76 81 86 91 96 101 106 mhz dbuv none 200nh 270nh 390nh
an383 rev. 0.8 55 a ppendix b?fm t ransmit e mbedded a ntenna i nterface m odel this application note describes the circuit required for interfacing the fm transmitter to a short monopole pcb trace or wire antenna. it is strongly recommend ed that customers follow these schematic and layout recommendations in their designs to optimize transmitter radiated power and noise performance. a representation of a typical application is shown in figure 36. figure 36. typical application electrically short vertical monopole antenna over an infinitely large ground plane radiated power from the fm transmitter is maximized when using a long wire antenna, resonated with a low loss tuning inductor and positioned vertically above an infini tely large ground plane. a longer antenna performs better than a shorter one because radiated power increases with antenna length. antennas should be 6 cm in length at a minimum to ensure that the fm transmitter can deliver suff icient current to the antenn a to meet maximum radiated power limits. a tuning inductor is required to resonate the antenna and should be low loss so that minimal current is dissipated in the inductor and delivered instead to the antenna. for practical purposes, the vertical monopole above an infinitely large ground plane is replaced with the requirement that the distance between the antenna and the ground and power planes be maximized. in summary, to maximize antenna radiated power: 1. maximize antenna length. 2. maximize antenna current. 3. maximize distance between the end of the antenna and the ground and power planes. si471x/2x tx antenna >10 cm pcb or wire l tune 120 nh q > 30
an383 56 rev. 0.8 electrically short vertical monopole antenna over an infinitely large ground plane the model of an electrically short vertical monopole antenna over an infinitely large ground plane is shown in figure 37. the term "electrica lly short" describes an antenna much shor ter than one waveleng th. our focus will be on antennas 6 to 15 cm long, whereas at 100 mhz a wavelength is approximately 3 m. figure 37. model of an electrically short vertical monopole antenna over an infinitely large ground plane x ant = antenna reactance r ant = antenna radiation resistance i ant = antenna current the antenna radiation resistance models the an tenna power dissipating el ement and is given as: , where l = meters, c = 3 x 10 8 m/s the radiated power is given as: , where l = meters, c = 3 x 10 8 m/s r ant x ant antenna model i ant r ant 20 2 ? fl c ------------ - ?? ?? 2 = p ant i 2 r ant i 2 20 2 ? fl c ------------ - ?? ?? 2 ==
an383 rev. 0.8 57 this equation shows that radiated power increases as the square of the antenna length and as the square of the delivered current. every effort should therefore be made to maximize the length of the antenna and maximize antenna current. minimizing circuit lo sses will maximize antenna current and can best be achieved by selecting a tuning inductor with a q > 30. note maximizing antenna curr ent is equivalent to maximizing antenna voltage, a point that will be discusse d later in this section. the antenna reactance models the antenna capacitance fo r electrically short monopol e antennas and is given as follows: where l = meters, c = 3 x 10 8 m/s this equation shows that antenna reactance decreases, and therefore capacitance increases, linearly with increasing antenna length. this capacitance should be kept in the range that can effectively be resonated by the tuning inductor. in practice this is easily ac hieved and is only mentioned for completeness. the following section, ? electrically short monopole interface model?, discusses the ranges of capacitance and inductance that should be expected. as the name suggests, the electrically short vertical monopole antenna over an infinite ground plane assumes an antenna oriented vertically, or perpendicularly, to a ground plane that is infinite in size. as the antenna implementation deviates from this model, the effect ive antenna length decreases, resulting in a decrease in radiated power. as a practical matter , the geometry of the antenna and gr ound plane is dictated by physical dimensions of the device and the clos est approximation to the ideal model is achieved by keeping the antenna as far away from ground and power planes as possible. this applies equally to a wire antenna and a pcb trace antenna. for brevity, the remainder of this document refers to this mode l as simply the "electrically short monopole." electrically short mono pole interface model the electrically short monopole model can be extended to incorporate the fm transmitter output buffer capacitance, external tuning inductor and pcb capaci tance as shown in figure 38. at lengths below 1/2 wavelength, the antenna reactance x ant is capacitive and is replaced with capacitance c ant . figure 38. simplified model of the electrically short monopole x ant 198c 2 ? fl ------------ - = l tune fm transmitter buffer pcb tuning inductor r buffer c buffer r tune c pcb r ant c ant antenna i buffer i ant
an383 58 rev. 0.8 c buffer = variable tuning capacitance (c tune ) + c on chip parasitic r buffer = variable tuning capacitor series resistance l tune = tuning inductance r tune = tuning inductor series resistance c pcb = pcb parasitic capacitance c ant = antenna capacitance r ant = antenna series resistance x ant is 1.6 k ? for a 6 cm antenna at 100 mhz and is approximated as follows: where l =0.06, f =100mhz, c=3x10 8 c ant is 1 pf at 100 mhz for x ant of 1.6 k ? and is given as follows: rant is 0.31 ? for a 6 cm antenna at 100 mhz and is approximated as follows: , where l =0.06, f =100mhz, c=3x10 8 qant is approximately 5000 for a 6 cm antenna at 100 mhz and is approximated as follows: the series resistances r buffer , r tune and r ant can be transformed to a parallel resistance over a narrow range of frequencies with the following equation if the q of each of the reactive elements c buffer , l tune , and c ant are known: the series inductance, l tune , can be transformed to a parallel inductance over a narrow range of frequencies if the q of l tune is known with the following approximation: x ant 198c 2 ? fl ------------ - = c ant 1 2 ? f x ant ------------- --------- - = r ant 20 2 ? fl c ------------ - ?? ?? 2 = q x ant r ant ------------- - = r p r s q 2 1 + ?? =
an383 rev. 0.8 59 for q >> 1 for sufficiently large q, the inductive element is approximately the same for a series and parallel model. the series capacitances c buffer and c ant can be transformed to a parallel capacitance over a narrow range of frequencies if the q of c buffer and c ant are known with the following approximation: for q >> 1 l p l s q 2 1 + q 2 ---------------- - l s ? = c p c s q 2 q 2 1 + ---------------- - c s ? =
an383 60 rev. 0.8 for sufficiently large q, the capacitive element is approximately the same for a series and parallel model. the circuit model shown in figure 38 can be represented as a parallel resonant rlc circuit by replacing the series models with equivalent parallel models as shown in figure 39. note that only the values of the resistances change appreciably. the parallel model for each circuit element is indicated with an asterisk. figure 39. equivalent rlc model of the electrically short vertical monopole c buffer = variable tuning capacitance (c tune ) + c onchip parasitic r buffer * = variable tuning capacitor parallel resistance l tune = tuning inductance r tune * = tuning inductor parallel resistance c pcb = pcb parasitic capacitance c ant = antenna capacitance r ant * = antenna parallel resistance c tune will range from 0.25 to 47.75 pf. c onchip parasitic is approximately 5 pf. therefore, c buffer will range from 5 to 53 pf. r buffer * will range from 1.2 to 1.6 k ? r tune * will be approximately than 2.3 k ? when l tune is 120 nh with a q > 30 c pcb should be 4 pf or less to allow sufficient range for c buffer to tune across the fm band. c ant will be approximately 1 pf. r ant * will be approximately 8 m ? for q ant = 5000 and is approximated as follows: l tune fm transmitter buffer pcb tuning inductor r buffer * c buffer r tune * c pcb r ant * c ant antenna i buffer v ant + - r ant *r ant q ant 2 1 + ?? =
an383 rev. 0.8 61 elements can be regrouped and the circuit model show n in figure 39 can be simplified as shown in figure 40. figure 40. simplified rlc model of the electrically short vertical monopole c p = c buffer || c pcb || c ant l tune = tuning inductance r p = r tune * || r buffer * r ant * = antenna parallel resistance c p will range from 10 to 58 pf. l tune should be 120 nh with a q > 30 to maintain r tune * > 2 k ? r p will be approximately 800 ? . r ant * will be approximately 8 m ? . figure 40 shows that in order to maximize antenna voltage v ant , and therefore radiated power, r p should be maximized by choosing an inductor with a q > 30 and r ant should be maximized by maximizing the antenna length. choosing tuning inductance the recommended value for the tuning inductance is 120 nh and it is based on a typical total parasitic capacitance of 10 pf. in the event where the parasitic capacitance differs quite significantly from this number, it may be necessary to make l tune lower or higher. the total capacitance needed to tune to a part icular frequency is given with this formula: actual ctune needed on the chip then can be calculated by subtracting all of the parasitic capacitance including the si471x on chip parasitic capacitance, pcb capacitance, and antenna capacitance. ctune = ctotal ? conchip parasitic ? cpcb ? cant l tune buffer, pcb, antenna buffer, inductor tuning inductor c p r ant * antenna r p i ant v ant + - ? 1 l.c -------- - = 2 ? f ?? 2 1 l.ctotal -------------------- =
an383 62 rev. 0.8 the actual ctune needed then has to be well wit hin the available range of ctune, which is: ctune min = 0.25 pf ctune max = 47.75 pf ctune can be read from the chip and the range will be 1?191. each number represents 0. 25 pf, so the range is 0.25 to 47.75 pf. example 1 conchip parasitic = 5 pf cpcb = 4 pf cant = 1 pf ctotal parasitic capacitance = 5 + 4 + 1 = 10 pf ltune = 120 nh desired fm frequency = 76?108 mhz at 76 mhz > ctotal = 37 pf, ctune = 37 ? 10 = 27 pf at 108 mhz > ctotal = 18 pf, ctune = 18 ? 10 = 8 pf in this case at the fm frequency of interest (76 mhz to 108 mhz), the needed ctune range (8?27 pf) is within the available ctune range on the chip (0.25?47.75 pf) which means that the 120 nh inductor value is a good choice. example 2 conchip parasitic = 5 pf cpcb = 10 pf cant = 1 pf ctotal parasitic capacitance = 5 + 10 + 1 = 16 pf at 76 mhz > ctotal = 37 pf, ctune = 37 ? 16 = 21 pf at 108 mhz > ctotal = 18 pf, ctune = 18 ? 16 = 2 pf in this case at 108 mhz even though ctune needed (2 pf ) is still higher than the min ctune (0.25 pf), it is not advisable to keep ltune at 120 nh. variation in the para sitic capacitance from the pcb and different components may result in the ctune needed to be eq ual or less than 0.25 pf. it is advi sable then to lower the ltune value to 100 nh. solution make ltune = 100 nh at 76 mhz > ctotal = 44 pf, ctune = 28 pf at 108 mhz > ctotal = 22 pf, ctune = 6 pf in this case the needed ctune range (6?28 pf) is well within the available ctune (0.25 to 47.75 pf).
an383 rev. 0.8 63 a ppendix c?am f errite l oop s tick a ntenna i nterface m odel this appendix describes how to interface a ferrite loop st ick antenna to the am receiver input. the application note begins with an overview of am ferrite loop antennas follo wed by the interface to a ferrite loop stick antenna. the last section of the application note presents designers wit h guidelines for designing ferrite loop stick antennas. am ferrite loop stick antenna overview an am antenna works on the basis of faraday's law. faraday 's law dictates that a vary ing magnetic field through a wire loop induces an emf (electro-motive force) in the loop and is expressed as: where ? = magnetic flux. the negative sign in equation indicates that the current generated in the loop is in a direction which generates a magnetic field that opposes the magnetic field causing t he induced emf. an am loop antenna is made of a single loop or many loops of a conducting material wrapped around an air core or a ferrite core. in the case of radio transmissions, the induced voltage represents the am signal being transmitted by a radio station as electromagnetic waves. a ferrite loop stick antenna is a coil wrapped around a fe rrite core. ferrite is a ferromagnetic material which does not display any magnetic properties till it is excited by a magnetic field. a ferr ite multiplies the applied magnetic field by a factor that is known as the ef fective permeability of the ferrite materi al. since the permeability of a ferrite material is orders of magnitude higher than air, the vo ltage induced in a loop antenna wound around a ferrite core is also orders of magnitude greater th an the voltage that would be induced in an air loop antenna of the same size. all ferrite loop stick antennas have an inductance associated with them and this can be expressed as: equation 3. trap frequency calculation where: l ant = antenna inductance k = permeability modifier constant r = relative permeability of ferrite rod o = permeability of air/free space n = number of turns in coil a = cross-sectional area of ferrite rod l r = length of ferrite rod in equation 3, r is the relative permeability of the ferrite rod. the rod dimensions play an important role in determining the relative perme ability of the rod. the permeability modifier co nstant is based on the ratio of ferrite rod length to the coil length. the re lative permeability of t he rod and the permeability modifier constant are combined together to yiel d the effective permeability of the antenna and ar e used to reduce equation 3 to the following: emf d ? dt ------ - ? = l ant k ? r ? o n 2 a l r -------------- ------------ =
an383 64 rev. 0.8 equation 4. ferrite loop inductance calculation where e = effective relative permeability of antenna signal receiving capability of an antenna is defined by its antenna height. antenna he ight of a lo op antenna is derived from equation by replacing t he flux with the inner product of the ma gnetic field and the surface area of the coil and is expressed as follows: equation 5. simplified ferrite loop inductance calculation where: h e = effective antenna height n = number of turns in coil a = cross-sectional area of ferrite rod e = relative effective permeability of antenna ? = wavelength of signal equation 6 is used to rewrite the antenna hei ght in terms of antenna inductance as follows: equation 6. effective antenna height calculation where: f = signal frequency l ant = antenna inductance l r = length of ferrite rod c = speed of light o = permeability of air/free space n = number of turns in coil equation 6 tells us the relationship between antenna hei ght and the factors that affect antenna height. the induced voltage can be calculated simply by multiplying the antenn a height with the electric fi eld strength for an am signal (denoted by e) with dimensions of volts/unit length. equation 7 expresses this relationship: equation 7. induced voltage calculation l ? o ? e n 2 a i r ------------- ----------- = h e 2 ? na ? e ? ------------- --------- = h e 2 ? fl ant l r c ? o n ------------- --------- - = v induced e 2 ? fl ant l r c ? o n -------------- -------- - ? =
an383 rev. 0.8 65 am ferrite loop stick antenna interface the front-end of the am rx is an lc tuned circuit, the pu rpose of which is to gain the received signal from any tuned am station. the lc tuned circuit comprises of an inductance which comes form the attached antenna and a variable capacitance that is provided by a tunable capa citor inside the am rx. figure 41 shows the model circuit for the front-end of a loop antenna attached to the am rx. figure 41. am front-end with ferrite loop antenna the purpose of the variable tuning capacitor (c tune ) is to resonate the front-end such that the resonance frequency is the same as the frequency of the am station one wants to listen to. in order to tune to a specific station, the c tune capacitor is adjusted such that the front-end achieves resonance and the voltage received from the antenna is gained up before entering the am front end. c tune also has a stray resistance (r c-tune ) associated with it which affects the q of the tuning capacitor. the q of the on-chip tuning capacitor is given as follows: equation 8. on-chip capacitor q calculation where: q c-tune = quality factor of on-chip tuning capacitor ? o = resonance frequency r c-tune = stray resistance of on-chip tuning capacitor c tune = capacitance of on-chip tuning capacitor the reason the stray resistance is shown as a variable re sistance in figure 41 is because the on-chip capacitor is implemented as a bank of capacitors and as capacitors are switched in or out, the stray resistance also changes. the purpose of the variable resistor (r de-q ) in the front-end is to reduce the gain of the front-end circuit. being able to reduce gain is helpful if the received signal is too strong and does not need to be gained by the front-end circuit. it will be shown later that the gain of the circuit at resonance is equal to q of the circuit and is di rectly proportional to the total resistance between the am input and ground. since the variable resistor (r de-q ) is part of the total resistance between the am input and ground and is the only va riable resistor, it can be stated that the gain of the front-end can be controlled by the de-q resistor. c pcb is the capacitance associated with the pcb. r lna and c lna are the impedance and the capacitance from the low-noise amplifier (lna). the circuit in figure 41 can be reduced to a si mpler circuit by assuming that the circuit is tuned to a certain am station and the front-end is in resonance, which allows the conversion of r ant to a parallel resistance and r c-tune to a parallel capacitance. the new circuit is shown in figure 42: pcb am front end v ant l ant r ant c pcb r de-q c tune c lna r lna ferrite loop stick antenna r c-tune c ant q c tune ? 1 ? o r c tune ? c tune ----------------- -------------- ------------ =
an383 66 rev. 0.8 figure 42. am front-end with series antenna and on-chip resistances converted to parallel resistances the circuit can be further simplified because at resonance r de-q and c tune are fixed and the resistance and capacitances can be lumped together. the new circuit is shown in figure 43. figure 43. circuit elements have been lumped together to simplify circuit further analyzing this circuit is a mathematical exercise and is not covered in this document. it can be easily shown that the resonant frequency for this circuit is equal to the following: equation 9. resonant frequency calculation the q of the circuit at resonance can be calculated by finding the magnitude of the transfer function and substituting ? with ? resonance . the q of the circuit at resonance is expressed as follows: equation 10. overall circuit q calculation pcb am front end v ant r p-ant c pcb r de-q c tune c lna r lna loop antenna r pc-tune l ant c ant where: 1/r to ta l =1/r p-ant +1/r de-q +1/r pc-tune +1/r lna c to t a l =c ant +c pcb +c tune +c lna c total r total v ant l ant ? resonance 1 l ant c total ---------------- -------------- = q circuit r total l ant c total --------------- =
an383 rev. 0.8 67 d ocument c hange l ist revision 0.3 to revision 0.4 ? updated "2. si47xx 3x3 mm qfn schematic and layout" on page 5 with latest recommendation on schematic, layout and design guidelines. ? added "6. cable antenna for fm transmit on txo and receive on lpi (si4704/05/06/1x/2x only)" on page 34. ? added "7. whip antenna for fm/wb receiver on fmi (si4707/3x only)" on page 37. ? updated "8. ferrite loop antenna for am/lw receive on ami (si4730/31/34/35/36/37 only)" on page 39 with ferrite loop antenna pictures, recommendation and vendor information. ? updated "9. air loop antenna for am/lw receive on ami (si4730/31/34/35/36/37 on ly)" on page 42 with air loop antenna pictures, transformer re commendation and vendor information. ? added "10. whip antenna for sw receive on ami (si4734/35 only)" on page 45. revision 0.4 to revision 0.5 ? updated "2. si47xx 3x3 mm qfn schematic and layout" on page 5 with latest recommendation on schematic, layout and design guidelines. ? added "4. cable antenna for fm receive on fmi (si470x/2x/3x/8x only)" on page 22. ? updated "5. embedded antenna for fm transmit on txo and receive on lpi (si470 4/05/06/1x/2x only)" on page 25. ? added "6. cable antenna for fm transmit on txo and receive on lpi (si4704/05/06/1x/2x only)" on page 34. ? added "7. whip antenna for fm/wb receiver on fmi (si4707/3x only)" on page 37. ? updated "8. ferrite loop antenna for am/lw receive on ami (si4730/31/34/35/36/37 only)" on page 39 with vendor information. ? updated "9. air loop antenna for am/lw receive on am i (si4730/31/34/35/36/37 only)" on page 42 with vendor information. revision 0.5 to revision 0.6 ? added note to ?2.1. si47xx 3x3 mm design? and updated pin names and pin numbers on page 5. revision 0.6 to revision 0.8 ? removed note from section ?2.1. si47xx 3x3 mm design?.
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an383 68 rev. 0.8 n otes :

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